Re: igc: I226-V does not wake from S5, PHPM D3 link-disable bits never cleared

["Ruinskiy, Dima" <dima.ruinskiy@intel.com>]

On 17/10/2026 13:14, Michael Serajnik wrote:

> What I see:
> - `ethtool eno1` shows "Supports Wake-on: pumbg" and "Wake-on: g".
> - BIOS: ErP disabled, Power On By PCI-E enabled.
> - /proc/acpi/wakeup has the NIC and every port on its path enabled.
> - After `systemctl poweroff`, the port LEDs go dark, the switch sees
>    no link, and a magic packet from the same subnet does not wake the
>    machine.
> 
> Register read:
> With igc unbound (strict devmem refuses the mmap while it is bound),
> I read BAR0 + 0xE14 (IGC_I225_PHPM):
> 
>    PHPM = 0x00045298
>    DIS_1000_D3 (0x0008), DIS_100_D3 (0x0200), DIS_2500_D3 (0x1000)
>    are all set (mask 0x1208).
> 
> As a sanity check, RAL0 (0x5400) read 0x62e7fcbc, which matches the
> MAC address bc:fc:e7:62:d6:2f.
> 
> These bits come from the NIC's NVM, not from the board firmware, and
> FreeBSD bug 282140 (below) reports the same link-disable bits on other
> hardware, so I do not expect a BIOS update to change this. [1]
> 
> With all three speeds disabled in D3, the PHY has no link while the
> device is in D3, so the magic packet never reaches the MAC, however
> WUFC is programmed. In mainline igc, `__igc_shutdown()` sets WUC,
> WUFC and CTRL.ADVD3WUC and calls `igc_power_up_link()`, but nothing
> in the driver clears these PHPM bits, and igc defines neither the
> bits nor a D3 LPLU operation.

Hi Michael,

With these bits cleared, the link should resolve to the lowest, 10Mbps 
speed. In recent years, an increasing number of switches stopped 
supporting 10Mbps, so we have been receiving reports of similar problems 
from time to time.

I think I can fix it in the driver, but to double-check that the problem 
is indeed this, and not something else in the wake-from-shutdown path, 
could you try to reproduce with a different link partner (switch or 
back-to-back) that is known to support 10Mbps link speed?

Thanks!
--Dima