From: sunil.kovvuri@gmail.com
To: netdev@vger.kernel.org
Cc: davem@davemloft.net, Jerin Jacob <jerinj@marvell.com>,
Pavan Nikhilesh <pbhagavatula@marvell.com>,
Sunil Goutham <sgoutham@marvell.com>
Subject: [PATCH 07/15] octeontx2-af: add debug msgs for NIX block errors
Date: Sun, 17 Nov 2019 21:44:18 +0530 [thread overview]
Message-ID: <1574007266-17123-8-git-send-email-sunil.kovvuri@gmail.com> (raw)
In-Reply-To: <1574007266-17123-1-git-send-email-sunil.kovvuri@gmail.com>
From: Jerin Jacob <jerinj@marvell.com>
Added debug messages for NIX_AF_RVU_INT, NIX_AF_ERR_INT and NIX_AF_RAS
error AF interrupts.
These will help in detecting issues wrt AQ instruction faults,
LF misconfiguration, NPC MCAM entry trying to forward pkt to PF_FUNC
with no NIXLF mapped etc.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Sunil Goutham <sgoutham@marvell.com>
---
drivers/net/ethernet/marvell/octeontx2/af/rvu.c | 5 +
drivers/net/ethernet/marvell/octeontx2/af/rvu.h | 2 +
.../net/ethernet/marvell/octeontx2/af/rvu_nix.c | 202 +++++++++++++++++++++
.../net/ethernet/marvell/octeontx2/af/rvu_struct.h | 10 +
4 files changed, 219 insertions(+)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
index a13a055..6e4d5b8 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
@@ -2126,6 +2126,7 @@ static void rvu_unregister_interrupts(struct rvu *rvu)
int irq;
rvu_npa_unregister_interrupts(rvu);
+ rvu_nix_unregister_interrupts(rvu);
/* Disable the Mbox interrupt */
rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1C,
@@ -2339,6 +2340,10 @@ static int rvu_register_interrupts(struct rvu *rvu)
if (ret)
goto fail;
+ ret = rvu_nix_register_interrupts(rvu);
+ if (ret)
+ goto fail;
+
return 0;
fail:
rvu_unregister_interrupts(rvu);
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
index a6fe840..9f3d817 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
@@ -465,6 +465,8 @@ void rvu_nix_freemem(struct rvu *rvu);
int rvu_get_nixlf_count(struct rvu *rvu);
void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf);
int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf);
+int rvu_nix_register_interrupts(struct rvu *rvu);
+void rvu_nix_unregister_interrupts(struct rvu *rvu);
/* NPC APIs */
int rvu_npc_init(struct rvu *rvu);
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
index 10b49e5..f1201e0 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
@@ -3407,3 +3407,205 @@ int rvu_mbox_handler_nix_lso_format_cfg(struct rvu *rvu,
return 0;
}
+
+static irqreturn_t rvu_nix_af_rvu_intr_handler(int irq, void *rvu_irq)
+{
+ struct rvu *rvu = (struct rvu *)rvu_irq;
+ int blkaddr;
+ u64 intr;
+
+ blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, 0);
+ if (blkaddr < 0)
+ return IRQ_NONE;
+
+ intr = rvu_read64(rvu, blkaddr, NIX_AF_RVU_INT);
+
+ if (intr & BIT_ULL(0))
+ dev_err(rvu->dev, "NIX: Unmapped slot error\n");
+
+ /* Clear interrupts */
+ rvu_write64(rvu, blkaddr, NIX_AF_RVU_INT, intr);
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t rvu_nix_af_err_intr_handler(int irq, void *rvu_irq)
+{
+ struct rvu *rvu = (struct rvu *)rvu_irq;
+ int blkaddr;
+ u64 intr;
+
+ blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, 0);
+ if (blkaddr < 0)
+ return IRQ_NONE;
+
+ intr = rvu_read64(rvu, blkaddr, NIX_AF_ERR_INT);
+
+ if (intr & BIT_ULL(14))
+ dev_err(rvu->dev, "NIX: Memory fault on NIX_AQ_INST_S read\n");
+
+ if (intr & BIT_ULL(13))
+ dev_err(rvu->dev, "NIX: Memory fault on NIX_AQ_RES_S write\n");
+
+ if (intr & BIT_ULL(12))
+ dev_err(rvu->dev, "NIX: AQ doorbell error\n");
+
+ if (intr & BIT_ULL(6))
+ dev_err(rvu->dev, "NIX: Rx on unmapped PF_FUNC\n");
+
+ if (intr & BIT_ULL(5))
+ dev_err(rvu->dev, "NIX: Rx multicast replication error\n");
+
+ if (intr & BIT_ULL(4))
+ dev_err(rvu->dev, "NIX: Memory fault on NIX_RX_MCE_S read\n");
+
+ if (intr & BIT_ULL(3))
+ dev_err(rvu->dev, "NIX: Memory fault on multicast WQE read\n");
+
+ if (intr & BIT_ULL(2))
+ dev_err(rvu->dev, "NIX: Memory fault on mirror WQE read\n");
+
+ if (intr & BIT_ULL(1))
+ dev_err(rvu->dev, "NIX: Memory fault on mirror pkt write\n");
+
+ if (intr & BIT_ULL(0))
+ dev_err(rvu->dev, "NIX: Memory fault on multicast pkt write\n");
+
+ /* Clear interrupts */
+ rvu_write64(rvu, blkaddr, NIX_AF_ERR_INT, intr);
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t rvu_nix_af_ras_intr_handler(int irq, void *rvu_irq)
+{
+ struct rvu *rvu = (struct rvu *)rvu_irq;
+ int blkaddr;
+ u64 intr;
+
+ blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, 0);
+ if (blkaddr < 0)
+ return IRQ_NONE;
+
+ intr = rvu_read64(rvu, blkaddr, NIX_AF_RAS);
+
+ if (intr & BIT_ULL(34))
+ dev_err(rvu->dev, "NIX: Poisoned data on NIX_AQ_INST_S read\n");
+
+ if (intr & BIT_ULL(33))
+ dev_err(rvu->dev, "NIX: Poisoned data on NIX_AQ_RES_S write\n");
+
+ if (intr & BIT_ULL(32))
+ dev_err(rvu->dev, "NIX: Poisoned data on HW context read\n");
+
+ if (intr & BIT_ULL(4))
+ dev_err(rvu->dev, "NIX: Poisoned data on packet read from mirror buffer\n");
+
+ if (intr & BIT_ULL(3))
+ dev_err(rvu->dev, "NIX: Poisoned data on packet read from multicast buffer\n");
+
+ if (intr & BIT_ULL(2))
+ dev_err(rvu->dev, "NIX: Poisoned data on WQE read from mirror buffer\n");
+
+ if (intr & BIT_ULL(1))
+ dev_err(rvu->dev, "NIX: Poisoned data on WQE read from multicast buffer\n");
+
+ if (intr & BIT_ULL(0))
+ dev_err(rvu->dev, "NIX: Poisoned data on NIX_RX_MCE_S read\n");
+
+ /* Clear interrupts */
+ rvu_write64(rvu, blkaddr, NIX_AF_RAS, intr);
+ return IRQ_HANDLED;
+}
+
+static bool rvu_nix_af_request_irq(struct rvu *rvu, int blkaddr, int offset,
+ const char *name, irq_handler_t fn)
+{
+ int rc;
+
+ WARN_ON(rvu->irq_allocated[offset]);
+ rvu->irq_allocated[offset] = false;
+ sprintf(&rvu->irq_name[offset * NAME_SIZE], name);
+ rc = request_irq(pci_irq_vector(rvu->pdev, offset), fn, 0,
+ &rvu->irq_name[offset * NAME_SIZE], rvu);
+ if (rc)
+ dev_warn(rvu->dev, "Failed to register %s irq\n", name);
+ else
+ rvu->irq_allocated[offset] = true;
+
+ return rvu->irq_allocated[offset];
+}
+
+int rvu_nix_register_interrupts(struct rvu *rvu)
+{
+ int blkaddr, base;
+ bool rc;
+
+ blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, 0);
+ if (blkaddr < 0)
+ return blkaddr;
+
+ /* Get NIX AF MSIX vectors offset. */
+ base = rvu_read64(rvu, blkaddr, NIX_PRIV_AF_INT_CFG) & 0x3ff;
+ if (!base) {
+ dev_warn(rvu->dev,
+ "Failed to get NIX_AF_INT vector offsets\n");
+ return 0;
+ }
+
+ /* Register and enable NIX_AF_RVU_INT interrupt */
+ rc = rvu_nix_af_request_irq(rvu, blkaddr, base + NIX_AF_INT_VEC_RVU,
+ "NIX_AF_RVU_INT",
+ rvu_nix_af_rvu_intr_handler);
+ if (!rc)
+ goto err;
+ rvu_write64(rvu, blkaddr, NIX_AF_RVU_INT_ENA_W1S, ~0ULL);
+
+ /* Register and enable NIX_AF_ERR_INT interrupt */
+ rc = rvu_nix_af_request_irq(rvu, blkaddr, base + NIX_AF_INT_VEC_AF_ERR,
+ "NIX_AF_ERR_INT",
+ rvu_nix_af_err_intr_handler);
+ if (!rc)
+ goto err;
+ rvu_write64(rvu, blkaddr, NIX_AF_ERR_INT_ENA_W1S, ~0ULL);
+
+ /* Register and enable NIX_AF_RAS interrupt */
+ rc = rvu_nix_af_request_irq(rvu, blkaddr, base + NIX_AF_INT_VEC_POISON,
+ "NIX_AF_RAS",
+ rvu_nix_af_ras_intr_handler);
+ if (!rc)
+ goto err;
+ rvu_write64(rvu, blkaddr, NIX_AF_RAS_ENA_W1S, ~0ULL);
+
+ return 0;
+err:
+ rvu_nix_unregister_interrupts(rvu);
+ return rc;
+}
+
+void rvu_nix_unregister_interrupts(struct rvu *rvu)
+{
+ int blkaddr, offs, i;
+
+ blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, 0);
+ if (blkaddr < 0)
+ return;
+
+ offs = rvu_read64(rvu, blkaddr, NIX_PRIV_AF_INT_CFG) & 0x3ff;
+ if (!offs)
+ return;
+
+ rvu_write64(rvu, blkaddr, NIX_AF_RVU_INT_ENA_W1C, ~0ULL);
+ rvu_write64(rvu, blkaddr, NIX_AF_ERR_INT_ENA_W1C, ~0ULL);
+ rvu_write64(rvu, blkaddr, NIX_AF_RAS_ENA_W1C, ~0ULL);
+
+ if (rvu->irq_allocated[offs + NIX_AF_INT_VEC_RVU]) {
+ free_irq(pci_irq_vector(rvu->pdev, offs + NIX_AF_INT_VEC_RVU),
+ rvu);
+ rvu->irq_allocated[offs + NIX_AF_INT_VEC_RVU] = false;
+ }
+
+ for (i = NIX_AF_INT_VEC_AF_ERR; i < NIX_AF_INT_VEC_CNT; i++)
+ if (rvu->irq_allocated[offs + i]) {
+ free_irq(pci_irq_vector(rvu->pdev, offs + i), rvu);
+ rvu->irq_allocated[offs + i] = false;
+ }
+}
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h
index 2940b6d..8fd256e 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h
@@ -70,6 +70,16 @@ enum npa_af_int_vec_e {
NPA_AF_INT_VEC_CNT = 0x5,
};
+/* NIX Admin function Interrupt Vector Enumeration */
+enum nix_af_int_vec_e {
+ NIX_AF_INT_VEC_RVU = 0x0,
+ NIX_AF_INT_VEC_GEN = 0x1,
+ NIX_AF_INT_VEC_AQ_DONE = 0x2,
+ NIX_AF_INT_VEC_AF_ERR = 0x3,
+ NIX_AF_INT_VEC_POISON = 0x4,
+ NIX_AF_INT_VEC_CNT = 0x5,
+};
+
/**
* RVU PF Interrupt Vector Enumeration
*/
--
2.7.4
next prev parent reply other threads:[~2019-11-17 16:15 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-17 16:14 [PATCH 00/15] octeontx2-af: SSO, TIM HW blocks and other config support sunil.kovvuri
2019-11-17 16:14 ` [PATCH 01/15] octeontx2-af: Interface backpressure configuration support sunil.kovvuri
2019-11-18 21:12 ` Jakub Kicinski
2019-11-19 7:30 ` Sunil Kovvuri
2019-11-17 16:14 ` [PATCH 02/15] octeontx2-af: Add support for importing firmware data sunil.kovvuri
2019-11-18 21:28 ` Jakub Kicinski
2019-11-19 7:31 ` Sunil Kovvuri
2019-11-19 21:38 ` Jakub Kicinski
2019-11-20 17:27 ` Sunil Kovvuri
2019-11-19 0:01 ` kbuild test robot
2019-11-22 19:37 ` kbuild test robot
2019-11-17 16:14 ` [PATCH 03/15] octeontx2-af: Cleanup CGX config permission checks sunil.kovvuri
2019-11-17 18:33 ` David Miller
2019-11-19 7:33 ` Sunil Kovvuri
2019-11-17 16:14 ` [PATCH 04/15] octeontx2-af: Ingress and egress pause frame configuration sunil.kovvuri
2019-11-18 21:33 ` Jakub Kicinski
2019-11-17 16:14 ` [PATCH 05/15] octeontx2-af: Set discovery ID for RVUM block sunil.kovvuri
2019-11-17 16:14 ` [PATCH 06/15] octeontx2-af: add debug msgs for NPA block errors sunil.kovvuri
2019-11-17 16:14 ` sunil.kovvuri [this message]
2019-11-17 16:14 ` [PATCH 08/15] octeontx2-af: Add SSO unit support to the AF driver sunil.kovvuri
2019-11-17 16:14 ` [PATCH 09/15] octeontx2-af: Config support for per HWGRP thresholds sunil.kovvuri
2019-11-17 16:14 ` [PATCH 10/15] octeontx2-af: add debug msgs for SSO block errors sunil.kovvuri
2019-11-17 16:14 ` [PATCH 11/15] octeontx2-af: add debugfs support for sso sunil.kovvuri
2019-11-17 16:14 ` [PATCH 12/15] octeontx2-af: Add TIM unit support sunil.kovvuri
2019-11-17 18:36 ` David Miller
2019-11-19 7:32 ` Sunil Kovvuri
2019-11-17 16:14 ` [PATCH 13/15] octeontx2-af: verify ingress channel in MCAM entry sunil.kovvuri
2019-11-17 16:14 ` [PATCH 14/15] octeontx2-af: NPC Tx parsed data key extraction profile sunil.kovvuri
2019-11-17 16:14 ` [PATCH 15/15] octeontx2-af: Support to get CGX link info like current speed, fec etc sunil.kovvuri
2019-11-18 21:49 ` Jakub Kicinski
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