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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , Daniel Machon , , , , Date: Fri, 23 Jan 2026 16:12:18 +0100 In-Reply-To: References: <20260123-phy_micrel_add_support_for_lan9645x_internal_phy-v1-1-8484b1a5a7fd@microchip.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.44.4-0ubuntu2.1 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Hi Oleksij, On Fri, 2026-01-23 at 10:55 +0100, Oleksij Rempel wrote: >=20 > Hi Jens, >=20 > On Fri, Jan 23, 2026 at 08:50:55AM +0100, Jens Emil Schulz =C3=98stergaar= d wrote: > > LAN9645X is a family of switch chips with 5 internal copper phys. The > > internal PHY is based on parts of LAN8832. This is a low-power, single > > port triple-speed (10BASE-T/100BASE-TX/1000BASE-T) ethernet physical > > layer transceiver (PHY) that supports transmission and reception of dat= a > > on standard CAT-5, as well as CAT-5e and CAT-6 Unshielded Twisted > > Pair (UTP) cables. > >=20 > > Add support for the internal PHY of the lan9645x chip family. >=20 > Looks like interesting switch for our use cases :) >=20 > > Reviewed-by: Steen Hegelund > > Reviewed-by: Daniel Machon > > Signed-off-by: Jens Emil Schulz =C3=98stergaard > > --- > > =C2=A0drivers/net/phy/micrel.c=C2=A0=C2=A0 | 142 ++++++++++++++++++++++= +++++++++++++++++++++++ > > =C2=A0include/linux/micrel_phy.h |=C2=A0=C2=A0 1 + > > =C2=A02 files changed, 143 insertions(+) > >=20 > > diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c > > index 225d4adf28be..7f47f7987067 100644 > > --- a/drivers/net/phy/micrel.c > > +++ b/drivers/net/phy/micrel.c > > @@ -6502,6 +6502,132 @@ static void lan8842_get_phy_stats(struct phy_de= vice *phydev, > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 stats->tx_errors =3D priv->phy_stats.tx_= errors; > > =C2=A0} > >=20 > > +#define LAN9645X_DAC_ICAS_AMP_POWER_DOWN=C2=A0=C2=A0=C2=A0=C2=A0 0x47 > > +#define LAN9645X_BTRX_QBIAS_POWER_DOWN=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0x46 > > +#define LAN9645X_TX_LOW_I_CH_CD_POWER_MGMT=C2=A0=C2=A0 0x45 > > +#define LAN9645X_TX_LOW_I_CH_B_POWER_MGMT=C2=A0=C2=A0=C2=A0 0x44 > > +#define LAN9645X_TX_LOW_I_CH_A_POWER_MGMT=C2=A0=C2=A0=C2=A0 0x43 >=20 > > +static const struct lanphy_reg_data force_dac_tx_errata[] =3D { > > +=C2=A0=C2=A0=C2=A0=C2=A0 /* Force channel A/B/C/D TX on */ > > +=C2=A0=C2=A0=C2=A0=C2=A0 { LAN8814_PAGE_POWER_REGS, > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 LAN9645X_DAC_ICAS_AMP_POWER_DOWN, > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0 }, > > +=C2=A0=C2=A0=C2=A0=C2=A0 /* Force channel A/B/C/D QBias on */ > > +=C2=A0=C2=A0=C2=A0=C2=A0 { LAN8814_PAGE_POWER_REGS, > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 LAN9645X_BTRX_QBIAS_POWER_DOWN, > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0xaa }, > > +=C2=A0=C2=A0=C2=A0=C2=A0 /* tx low I on channel C/D overwrite */ > > +=C2=A0=C2=A0=C2=A0=C2=A0 { LAN8814_PAGE_POWER_REGS, > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 LAN9645X_TX_LOW_I_CH_CD_POWER_MGM= T, > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0xbfff }, > > +=C2=A0=C2=A0=C2=A0=C2=A0 /* channel B low I overwrite */ > > +=C2=A0=C2=A0=C2=A0=C2=A0 { LAN8814_PAGE_POWER_REGS, > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 LAN9645X_TX_LOW_I_CH_B_POWER_MGMT= , > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0xabbf }, > > +=C2=A0=C2=A0=C2=A0=C2=A0 /* channel A low I overwrite */ > > +=C2=A0=C2=A0=C2=A0=C2=A0 { LAN8814_PAGE_POWER_REGS, > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 LAN9645X_TX_LOW_I_CH_A_POWER_MGMT= , > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0xbd3f }, > > +}; >=20 > It looks like this erratum not publicly documented. At least not here: > https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDoc= uments/Errata/LAN9645xS- > LAN9645xF-Errata-DS80001187.pdf >=20 > re there more information about it? Can it be described in the comment? >=20 You are right, I think they ought to be documented in the official erratas list with a more thorough description. I will get a hold of the right people and ask them to add it. > > + > > +static int lan9645x_config_init(struct phy_device *phydev) > > +{ > > +=C2=A0=C2=A0=C2=A0=C2=A0 int ret; > > + > > +=C2=A0=C2=A0=C2=A0=C2=A0 /* Apply erratas. */ > > +=C2=A0=C2=A0=C2=A0=C2=A0 ret =3D lan8842_erratas(phydev); > > +=C2=A0=C2=A0=C2=A0=C2=A0 if (ret < 0) > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 return ret; > > + > > +=C2=A0=C2=A0=C2=A0=C2=A0 return lanphy_write_reg_data(phydev, force_da= c_tx_errata, > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ARRAY_SIZE(force_dac= _tx_errata)); > > +} > > + > > +static int lan9645x_suspend(struct phy_device *phydev) > > +{ > > +=C2=A0=C2=A0=C2=A0=C2=A0 int aneg_en_state, ret; > > + > > +=C2=A0=C2=A0=C2=A0=C2=A0 /* Software workaround from design to handle = SPD. SPD will stop AFE > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * clock from AFE port, which makes the = system MAC fifo unable to flush. > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * The workaround is to restart ANEG and= wait for flush, before issuing > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * software power down. > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 */ > > +=C2=A0=C2=A0=C2=A0=C2=A0 aneg_en_state =3D phy_read(phydev, MII_BMCR) = & BMCR_ANENABLE; > > + > > +=C2=A0=C2=A0=C2=A0=C2=A0 ret =3D phy_restart_aneg(phydev); > > +=C2=A0=C2=A0=C2=A0=C2=A0 if (ret) > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 return ret; > > + > > +=C2=A0=C2=A0=C2=A0=C2=A0 /* Allow time for system FIFO flush data */ > > +=C2=A0=C2=A0=C2=A0=C2=A0 usleep_range(8 * USEC_PER_MSEC, 12 * USEC_PER= _MSEC); >=20 > MAC and PHY power management are not always fully coupled (implementation > specific), are there other ways to sync them with each other, except of > unconditional sleep in the PHY driver. I expect that someone making > changes on the MAC driver may miss this nuance. >=20 The MAC side will be handled in a yet-to-be-sent DSA driver, which is also authored by my team. During development I was seeing issues where SPD sometimes causing interference on neighbouring PHYs. The PHY team came up with the tx dac errata and the aneg restart workaround as a solution. To my knowledge there was no alternative workaround, but I have reached out to the PHY team to make sure. If there is a better way to fix these issues, I will add it in the next version. > Best Regards, > Oleksij > -- > Pengutronix e.K.=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | > Steuerwalder Str. 21=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 | http://www.pengutronix.de/=C2=A0 | > 31137 Hildesheim, Germany=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | Phone: +49-5121-20= 6917-0=C2=A0=C2=A0=C2=A0 | > Amtsgericht Hildesheim, HRA 2686=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 | Fax:=C2=A0=C2=A0 +49-5121-206917-5555 | Thank you for the comments, Emil