From: patchwork-bot+netdevbpf@kernel.org
To: Ido Schimmel <idosch@nvidia.com>
Cc: netdev@vger.kernel.org, davem@davemloft.net, kuba@kernel.org,
pabeni@redhat.com, edumazet@google.com, petrm@nvidia.com,
mlxsw@nvidia.com
Subject: Re: [PATCH net] mlxsw: spectrum_cnt: Reorder counter pools
Date: Tue, 14 Jun 2022 14:10:15 +0000 [thread overview]
Message-ID: <165521581518.20153.5995266466532935010.git-patchwork-notify@kernel.org> (raw)
In-Reply-To: <20220613125017.2018162-1-idosch@nvidia.com>
Hello:
This patch was applied to netdev/net.git (master)
by Paolo Abeni <pabeni@redhat.com>:
On Mon, 13 Jun 2022 15:50:17 +0300 you wrote:
> From: Petr Machata <petrm@nvidia.com>
>
> Both RIF and ACL flow counters use a 24-bit SW-managed counter address to
> communicate which counter they want to bind.
>
> In a number of Spectrum FW releases, binding a RIF counter is broken and
> slices the counter index to 16 bits. As a result, on Spectrum-2 and above,
> no more than about 410 RIF counters can be effectively used. This
> translates to 205 netdevices for which L3 HW stats can be enabled. (This
> does not happen on Spectrum-1, because there are fewer counters available
> overall and the counter index never exceeds 16 bits.)
>
> [...]
Here is the summary with links:
- [net] mlxsw: spectrum_cnt: Reorder counter pools
https://git.kernel.org/netdev/net/c/4b7a632ac4e7
You are awesome, thank you!
--
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prev parent reply other threads:[~2022-06-14 14:10 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-13 12:50 [PATCH net] mlxsw: spectrum_cnt: Reorder counter pools Ido Schimmel
2022-06-14 14:10 ` patchwork-bot+netdevbpf [this message]
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