[PATCH net] mlxsw: spectrum_cnt: Reorder counter pools

[PATCH net] mlxsw: spectrum_cnt: Reorder counter pools

[Ido Schimmel]

From: Petr Machata <petrm@nvidia.com>

Both RIF and ACL flow counters use a 24-bit SW-managed counter address to
communicate which counter they want to bind.

In a number of Spectrum FW releases, binding a RIF counter is broken and
slices the counter index to 16 bits. As a result, on Spectrum-2 and above,
no more than about 410 RIF counters can be effectively used. This
translates to 205 netdevices for which L3 HW stats can be enabled. (This
does not happen on Spectrum-1, because there are fewer counters available
overall and the counter index never exceeds 16 bits.)

Binding counters to ACLs does not have this issue. Therefore reorder the
counter allocation scheme so that RIF counters come first and therefore get
lower indices that are below the 16-bit barrier.

Fixes: 98e60dce4da1 ("Merge branch 'mlxsw-Introduce-initial-Spectrum-2-support'")
Reported-by: Maksym Yaremchuk <maksymy@nvidia.com>
Signed-off-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
---
 drivers/net/ethernet/mellanox/mlxsw/spectrum_cnt.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_cnt.h b/drivers/net/ethernet/mellanox/mlxsw/spectrum_cnt.h
index a68d931090dd..15c8d4de8350 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_cnt.h
+++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_cnt.h
@@ -8,8 +8,8 @@
 #include "spectrum.h"
 
 enum mlxsw_sp_counter_sub_pool_id {
-	MLXSW_SP_COUNTER_SUB_POOL_FLOW,
 	MLXSW_SP_COUNTER_SUB_POOL_RIF,
+	MLXSW_SP_COUNTER_SUB_POOL_FLOW,
 };
 
 int mlxsw_sp_counter_alloc(struct mlxsw_sp *mlxsw_sp,
-- 
2.36.1

Re: [PATCH net] mlxsw: spectrum_cnt: Reorder counter pools

[patchwork-bot+netdevbpf]

Hello:

This patch was applied to netdev/net.git (master)
by Paolo Abeni <pabeni@redhat.com>:

On Mon, 13 Jun 2022 15:50:17 +0300 you wrote:
> From: Petr Machata <petrm@nvidia.com>
> 
> Both RIF and ACL flow counters use a 24-bit SW-managed counter address to
> communicate which counter they want to bind.
> 
> In a number of Spectrum FW releases, binding a RIF counter is broken and
> slices the counter index to 16 bits. As a result, on Spectrum-2 and above,
> no more than about 410 RIF counters can be effectively used. This
> translates to 205 netdevices for which L3 HW stats can be enabled. (This
> does not happen on Spectrum-1, because there are fewer counters available
> overall and the counter index never exceeds 16 bits.)
> 
> [...]

Here is the summary with links:
  - [net] mlxsw: spectrum_cnt: Reorder counter pools
    https://git.kernel.org/netdev/net/c/4b7a632ac4e7

You are awesome, thank you!
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