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[146.241.254.39]) by smtp.gmail.com with ESMTPSA id q20-20020a170906145400b009fc927023bcsm495253ejc.34.2023.11.30.01.55.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Nov 2023 01:55:36 -0800 (PST) Message-ID: <1716792a3881338b1a416b1f4dd85a9437746ec2.camel@redhat.com> Subject: Re: [PATCH v3] net: stmmac: fix FPE events losing From: Paolo Abeni To: Jianheng Zhang , Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Maxime Coquelin , Simon Horman , Andrew Halaney , Bartosz Golaszewski , Shenwei Wang , Johannes Zink , "Russell King (Oracle" , Jochen Henneberg , Voon Weifeng , Mohammad Athari Bin Ismail , Ong Boon Leong , Tan Tee Min Cc: "open list:STMMAC ETHERNET DRIVER" , "moderated list:ARM/STM32 ARCHITECTURE" , "moderated list:ARM/STM32 ARCHITECTURE" , open list , James Li , Martin McKenny Date: Thu, 30 Nov 2023 10:55:34 +0100 In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.46.4 (3.46.4-1.fc37) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Tue, 2023-11-28 at 05:56 +0000, Jianheng Zhang wrote: > The status bits of register MAC_FPE_CTRL_STS are clear on read. Using > 32-bit read for MAC_FPE_CTRL_STS in dwmac5_fpe_configure() and > dwmac5_fpe_send_mpacket() clear the status bits. Then the stmmac interrup= t > handler missing FPE event status and leads to FPE handshaking failure and > retries. > To avoid clear status bits of MAC_FPE_CTRL_STS in dwmac5_fpe_configure() > and dwmac5_fpe_send_mpacket(), add fpe_csr to stmmac_fpe_cfg structure to > cache the control bits of MAC_FPE_CTRL_STS and to avoid reading > MAC_FPE_CTRL_STS in those methods. >=20 > Fixes: 5a5586112b92 ("net: stmmac: support FPE link partner hand-shaking = procedure") > Reviewed-by: Serge Semin > Signed-off-by: Jianheng Zhang > --- > drivers/net/ethernet/stmicro/stmmac/dwmac5.c | 45 +++++++++-------= ------ > drivers/net/ethernet/stmicro/stmmac/dwmac5.h | 4 +- > .../net/ethernet/stmicro/stmmac/dwxgmac2_core.c | 3 +- > drivers/net/ethernet/stmicro/stmmac/hwif.h | 4 +- > drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 8 +++- > drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c | 1 + > include/linux/stmmac.h | 1 + > 7 files changed, 36 insertions(+), 30 deletions(-) >=20 > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac5.c b/drivers/net/e= thernet/stmicro/stmmac/dwmac5.c > index e95d35f..8fd1675 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac5.c > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac5.c > @@ -710,28 +710,22 @@ void dwmac5_est_irq_status(void __iomem *ioaddr, st= ruct net_device *dev, > } > } > =20 > -void dwmac5_fpe_configure(void __iomem *ioaddr, u32 num_txq, u32 num_rxq= , > +void dwmac5_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *c= fg, > + u32 num_txq, u32 num_rxq, > bool enable) > { > u32 value; > =20 > - if (!enable) { > - value =3D readl(ioaddr + MAC_FPE_CTRL_STS); > - > - value &=3D ~EFPE; > - > - writel(value, ioaddr + MAC_FPE_CTRL_STS); > - return; > + if (enable) { > + cfg->fpe_csr =3D EFPE; > + value =3D readl(ioaddr + GMAC_RXQ_CTRL1); > + value &=3D ~GMAC_RXQCTRL_FPRQ; > + value |=3D (num_rxq - 1) << GMAC_RXQCTRL_FPRQ_SHIFT; > + writel(value, ioaddr + GMAC_RXQ_CTRL1); > + } else { > + cfg->fpe_csr =3D 0; > } > - > - value =3D readl(ioaddr + GMAC_RXQ_CTRL1); > - value &=3D ~GMAC_RXQCTRL_FPRQ; > - value |=3D (num_rxq - 1) << GMAC_RXQCTRL_FPRQ_SHIFT; > - writel(value, ioaddr + GMAC_RXQ_CTRL1); > - > - value =3D readl(ioaddr + MAC_FPE_CTRL_STS); > - value |=3D EFPE; > - writel(value, ioaddr + MAC_FPE_CTRL_STS); > + writel(cfg->fpe_csr, ioaddr + MAC_FPE_CTRL_STS); > } > =20 > int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev) > @@ -741,6 +735,9 @@ int dwmac5_fpe_irq_status(void __iomem *ioaddr, struc= t net_device *dev) > =20 > status =3D FPE_EVENT_UNKNOWN; > =20 > + /* Reads from the MAC_FPE_CTRL_STS register should only be performed > + * here, since the status flags of MAC_FPE_CTRL_STS are "clear on read" > + */ > value =3D readl(ioaddr + MAC_FPE_CTRL_STS); > =20 > if (value & TRSP) { > @@ -766,19 +763,15 @@ int dwmac5_fpe_irq_status(void __iomem *ioaddr, str= uct net_device *dev) > return status; > } > =20 > -void dwmac5_fpe_send_mpacket(void __iomem *ioaddr, enum stmmac_mpacket_t= ype type) > +void dwmac5_fpe_send_mpacket(void __iomem *ioaddr, struct stmmac_fpe_cfg= *cfg, > + enum stmmac_mpacket_type type) > { > - u32 value; > + u32 value =3D cfg->fpe_csr; > =20 > - value =3D readl(ioaddr + MAC_FPE_CTRL_STS); > - > - if (type =3D=3D MPACKET_VERIFY) { > - value &=3D ~SRSP; > + if (type =3D=3D MPACKET_VERIFY) > value |=3D SVER; > - } else { > - value &=3D ~SVER; > + else if (type =3D=3D MPACKET_RESPONSE) > value |=3D SRSP; > - } > =20 > writel(value, ioaddr + MAC_FPE_CTRL_STS); > } It's unclear to me why it's not necessary to preserve the SVER/SRSP bits across MAC_FPE_CTRL_STS writes. I guess they are not part of the status bits? perhaps an explicit comment somewhere will help? Thanks Paolo