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Sun, 13 Jul 2025 08:31:48 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Sun, 13 Jul 2025 08:31:47 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Sun, 13 Jul 2025 08:31:47 -0700 Received: from hyd1358.marvell.com (unknown [10.29.37.11]) by maili.marvell.com (Postfix) with ESMTP id 131795B6941; Sun, 13 Jul 2025 08:31:42 -0700 (PDT) From: Subbaraya Sundeep To: , , , , , CC: , , , , , , , Subbaraya Sundeep Subject: [net-next PATCH 06/11] octeontx2-af: Skip NDC operations for cn20k Date: Sun, 13 Jul 2025 21:01:04 +0530 Message-ID: <1752420669-2908-7-git-send-email-sbhatta@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1752420669-2908-1-git-send-email-sbhatta@marvell.com> References: <1752420669-2908-1-git-send-email-sbhatta@marvell.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-Authority-Analysis: v=2.4 cv=N48pF39B c=1 sm=1 tr=0 ts=6873d164 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=Wb1JkmetP80A:10 a=M5GUcnROAAAA:8 a=GFmy-jf8mh29BVtaGncA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-ORIG-GUID: YqU8Jq5-7wGNLsrvVMmk2AdfxkEAJ7b1 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzEzMDEwOCBTYWx0ZWRfXzFeLVq3c9L2F fPVMSjGxLNnRmzVPgfIyHwSX8cfOUOdVHHav/gGVcG8hV/BRr7kMLFAOap4Ffl0Ttc8ge8qo4c5 moNn2s0hYtMntDCGNBUBvlMkwiM1eAxUIQo3BL3t0favdtQw3UotQHw+sdBrTwoy8kYSEaAQwc+ 3ePQVVRnaIU4dBC4R6dLw+fC6BfPK2jbhxBVSC4iLpn6NZZe96dWymR01TYkGYgFsO6fG0SKVVI 8P1TxjN9m5Z3LlyHNe3u+pHKrjicvJ5aF0qYOcb/PIatGVPR+s2x5IC4DoD9e90VFb9l1CONy6k oqAMTxz0Rl+/ozCzDgeJmcQmer2jA5WEjaDVXn7QKHi2ckC94mzXOT7pHqWp1JViOPdqPq1Cnou ME7y75dOjaaJeRBL+BbwQx2AfFFWCezrbzrsOUQx37txWCh415ozCEpiQLhjaYub6jdTMNA3 X-Proofpoint-GUID: YqU8Jq5-7wGNLsrvVMmk2AdfxkEAJ7b1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-13_01,2025-07-09_01,2025-03-28_01 From: Linu Cherian For cn20k, NPA block doesn't use the general purpose NDC (Near Coprocessor Bus Data cache Unit) for caching, hence skip the NDC related operations. Also refactor NDC configuration code to a helper function. Signed-off-by: Linu Cherian Signed-off-by: Subbaraya Sundeep --- .../marvell/octeontx2/af/rvu_debugfs.c | 3 ++ .../ethernet/marvell/octeontx2/af/rvu_npa.c | 29 ++++++++++++++----- 2 files changed, 24 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c index 296012a2f3de..7243592f0e43 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c @@ -2743,6 +2743,9 @@ static void rvu_dbg_npa_init(struct rvu *rvu) &rvu_dbg_npa_aura_ctx_fops); debugfs_create_file("pool_ctx", 0600, rvu->rvu_dbg.npa, rvu, &rvu_dbg_npa_pool_ctx_fops); + + if (is_cn20k(rvu->pdev)) /* NDC not appliable for cn20k */ + return; debugfs_create_file("ndc_cache", 0600, rvu->rvu_dbg.npa, rvu, &rvu_dbg_npa_ndc_cache_fops); debugfs_create_file("ndc_hits_miss", 0600, rvu->rvu_dbg.npa, rvu, diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c index 4f5ca5ab13a4..e2a33e46b48a 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c @@ -464,6 +464,23 @@ int rvu_mbox_handler_npa_lf_free(struct rvu *rvu, struct msg_req *req, return 0; } +static void npa_aq_ndc_config(struct rvu *rvu, struct rvu_block *block) +{ + u64 cfg; + + if (is_cn20k(rvu->pdev)) /* NDC not applicable to cn20k */ + return; + + /* Do not bypass NDC cache */ + cfg = rvu_read64(rvu, block->addr, NPA_AF_NDC_CFG); + cfg &= ~0x03DULL; +#ifdef CONFIG_NDC_DIS_DYNAMIC_CACHING + /* Disable caching of stack pages */ + cfg |= 0x10ULL; +#endif + rvu_write64(rvu, block->addr, NPA_AF_NDC_CFG, cfg); +} + static int npa_aq_init(struct rvu *rvu, struct rvu_block *block) { u64 cfg; @@ -479,14 +496,7 @@ static int npa_aq_init(struct rvu *rvu, struct rvu_block *block) rvu_write64(rvu, block->addr, NPA_AF_GEN_CFG, cfg); #endif - /* Do not bypass NDC cache */ - cfg = rvu_read64(rvu, block->addr, NPA_AF_NDC_CFG); - cfg &= ~0x03DULL; -#ifdef CONFIG_NDC_DIS_DYNAMIC_CACHING - /* Disable caching of stack pages */ - cfg |= 0x10ULL; -#endif - rvu_write64(rvu, block->addr, NPA_AF_NDC_CFG, cfg); + npa_aq_ndc_config(rvu, block); /* For CN10K NPA BATCH DMA set 35 cache lines */ if (!is_rvu_otx2(rvu)) { @@ -567,6 +577,9 @@ int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr) int bank, max_bank, line, max_line, err; u64 reg, ndc_af_const; + if (is_cn20k(rvu->pdev)) /* NDC not applicable to cn20k */ + return 0; + /* Set the ENABLE bit(63) to '0' */ reg = rvu_read64(rvu, blkaddr, NDC_AF_CAMS_RD_INTERVAL); rvu_write64(rvu, blkaddr, NDC_AF_CAMS_RD_INTERVAL, reg & GENMASK_ULL(62, 0)); -- 2.34.1