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Tue, 15 Jul 2025 10:02:43 -0700 (PDT) From: Subbaraya Sundeep To: , , , , pabeni4redhat.com@mx0b-0016f401.pphosted.com, CC: , , , , , , , Subbaraya Sundeep Subject: [net-next PATCH v2 06/11] octeontx2-af: Skip NDC operations for cn20k Date: Tue, 15 Jul 2025 22:31:59 +0530 Message-ID: <1752598924-32705-7-git-send-email-sbhatta@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1752598924-32705-1-git-send-email-sbhatta@marvell.com> References: <1752598924-32705-1-git-send-email-sbhatta@marvell.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-GUID: JIjq-_38BmMd-3KKE4TVSW9IEzqxE5t7 X-Proofpoint-ORIG-GUID: JIjq-_38BmMd-3KKE4TVSW9IEzqxE5t7 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE1MDE1NiBTYWx0ZWRfXwUymeaUV4j+X vHrp2Zbw+5ff7Hxtu3rJAYmgUQAoC/2yGgF7kUi3zN6GeHBty8HDwJ0lPPm39Rr423S2s6MHXeW 5FNHTIB8u3BwHWVX4g0px8YKUiYlAfJTi6oo1/+Qpg+pI6CcEMws/okh7bw7jmQeu508T6vEcug eaZ1Ib7+tG0no04FfPwI99NSdrW0/jctbYTts3amQ2i1AaQErUNVhl3qOBc1ie2H8t1uR/uT0lN ds1QGLvRw7BGGYUeV2247QunGV0czjr/+FhF8qiWeVY6fmIinQW2nwxDN2qR2DTLGXMKfqwMFcX Wm2CJ4YkDnywp6xwUhILsmmSLP7I2EKpTrqTBj3WERMKsK8RSauzOOI6x78jm3Q2nashB2ojUv9 WbFXO3LC+IzAFJZuPRlAMdmHvT0O1buCaOlx4TsmpUbPc1A1trtCblQCF+xnUk6SXTmZYpSf X-Authority-Analysis: v=2.4 cv=Pav/hjhd c=1 sm=1 tr=0 ts=687689b9 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=Wb1JkmetP80A:10 a=M5GUcnROAAAA:8 a=GFmy-jf8mh29BVtaGncA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-15_04,2025-07-15_02,2025-03-28_01 From: Linu Cherian For cn20k, NPA block doesn't use the general purpose NDC (Near Coprocessor Bus Data cache Unit) for caching, hence skip the NDC related operations. Also refactor NDC configuration code to a helper function. Signed-off-by: Linu Cherian Signed-off-by: Subbaraya Sundeep --- .../marvell/octeontx2/af/rvu_debugfs.c | 3 ++ .../ethernet/marvell/octeontx2/af/rvu_npa.c | 29 ++++++++++++++----- 2 files changed, 24 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c index 296012a2f3de..7243592f0e43 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c @@ -2743,6 +2743,9 @@ static void rvu_dbg_npa_init(struct rvu *rvu) &rvu_dbg_npa_aura_ctx_fops); debugfs_create_file("pool_ctx", 0600, rvu->rvu_dbg.npa, rvu, &rvu_dbg_npa_pool_ctx_fops); + + if (is_cn20k(rvu->pdev)) /* NDC not appliable for cn20k */ + return; debugfs_create_file("ndc_cache", 0600, rvu->rvu_dbg.npa, rvu, &rvu_dbg_npa_ndc_cache_fops); debugfs_create_file("ndc_hits_miss", 0600, rvu->rvu_dbg.npa, rvu, diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c index 4f5ca5ab13a4..e2a33e46b48a 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c @@ -464,6 +464,23 @@ int rvu_mbox_handler_npa_lf_free(struct rvu *rvu, struct msg_req *req, return 0; } +static void npa_aq_ndc_config(struct rvu *rvu, struct rvu_block *block) +{ + u64 cfg; + + if (is_cn20k(rvu->pdev)) /* NDC not applicable to cn20k */ + return; + + /* Do not bypass NDC cache */ + cfg = rvu_read64(rvu, block->addr, NPA_AF_NDC_CFG); + cfg &= ~0x03DULL; +#ifdef CONFIG_NDC_DIS_DYNAMIC_CACHING + /* Disable caching of stack pages */ + cfg |= 0x10ULL; +#endif + rvu_write64(rvu, block->addr, NPA_AF_NDC_CFG, cfg); +} + static int npa_aq_init(struct rvu *rvu, struct rvu_block *block) { u64 cfg; @@ -479,14 +496,7 @@ static int npa_aq_init(struct rvu *rvu, struct rvu_block *block) rvu_write64(rvu, block->addr, NPA_AF_GEN_CFG, cfg); #endif - /* Do not bypass NDC cache */ - cfg = rvu_read64(rvu, block->addr, NPA_AF_NDC_CFG); - cfg &= ~0x03DULL; -#ifdef CONFIG_NDC_DIS_DYNAMIC_CACHING - /* Disable caching of stack pages */ - cfg |= 0x10ULL; -#endif - rvu_write64(rvu, block->addr, NPA_AF_NDC_CFG, cfg); + npa_aq_ndc_config(rvu, block); /* For CN10K NPA BATCH DMA set 35 cache lines */ if (!is_rvu_otx2(rvu)) { @@ -567,6 +577,9 @@ int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr) int bank, max_bank, line, max_line, err; u64 reg, ndc_af_const; + if (is_cn20k(rvu->pdev)) /* NDC not applicable to cn20k */ + return 0; + /* Set the ENABLE bit(63) to '0' */ reg = rvu_read64(rvu, blkaddr, NDC_AF_CAMS_RD_INTERVAL); rvu_write64(rvu, blkaddr, NDC_AF_CAMS_RD_INTERVAL, reg & GENMASK_ULL(62, 0)); -- 2.34.1