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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Lama Kayal Subject: [PATCH net-next V3 1/3] net/mlx5e: SHAMPO, Cleanup reservation size formula Date: Mon, 21 Jul 2025 10:13:17 +0300 Message-ID: <1753081999-326247-2-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1753081999-326247-1-git-send-email-tariqt@nvidia.com> References: <1753081999-326247-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001E8:EE_|MN0PR12MB5836:EE_ X-MS-Office365-Filtering-Correlation-Id: 6d921274-e6c3-4d9f-159e-08ddc8262b9a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?SxeBQcFTuhKJrn64kxV0pnaj7tuq8VKVW6hu4Ud6nvE+bgMkv3UeQSYkG9r9?= =?us-ascii?Q?MzIjGpI7nkaNboufX6pIJl/6GXpq+w/MouShygxREyLwKh7+ABUI7tFTeoPd?= =?us-ascii?Q?txSMokLuCHVEiG+Tcm7h9aMd3E5qyh4lqc1pmCuiUarMlFkBIzFmDbYlNfgK?= =?us-ascii?Q?CjBavwZ75Mnf9Y7Q3E8o0/OBvVWgzFNw/LxrjSKmDDC3SmkXiV42ewYJMkjB?= =?us-ascii?Q?cAk7q0chvgkGVarLIMc8xO7h9hpzuE61vUZPa60NCZhw0dwesm3QoYhcOIIP?= =?us-ascii?Q?lL4n8X16ffbIdEBGOBrIEfoZnqdi73Yj0h3jY18o8K0tiCW+yGgdifEasxCC?= =?us-ascii?Q?sQA30H3FHw+y8VA2SPWhJdTEBnXqcMjnep05SPRuQWrXfKzOQNUukFOIlelg?= =?us-ascii?Q?S3ZT2bQScgcvfUMtoMygoQWn7uUD6tWSgzFow0zodn+bIBp40ihjQYMajHiM?= =?us-ascii?Q?yXhW4A+E0k5vblc2PVbu37o05GmSIBUfQ7OVcZrXcX7Lel2BiSmvlUwEW6gT?= =?us-ascii?Q?zjiYDdxj32/lV3nIoO9IERmosyIXKV1zFanT7WREgxE7/+Et7GTJLVgJfGHx?= =?us-ascii?Q?McLfOOad9WjSwil4WAVyS8q90PHxJ8bZPEmQCu8mibQbew23G+VLdVUnSR0r?= =?us-ascii?Q?vOJUfn1QjGlbT7By4RPrkXfYdkfGrT4klQoGH8Tq9mkGZoajjFCqqSLJKKK/?= =?us-ascii?Q?FxB8Q9S0aKHasHv4vqybxobgWoz7nwdgBCLG3Tt6cJNDB6ljtjQDS8TAfnaJ?= =?us-ascii?Q?NDtOr3FESJcCVfe9Obfv/snCQ2L0s4x4Yp2MdCNmWwaziHG5MsTIYXN8i2lH?= =?us-ascii?Q?Smlj0k2k0JTqAbrvtiFiSHPyxu1lYOOU3ub3LJuL+O9oaOjyJSW+aagru2Ga?= =?us-ascii?Q?ycJU83tw5JXF6fPuMmJ/YYXmf039cfISbWIIxiNaiaoQcMDi34qi3/5BQT6b?= =?us-ascii?Q?uADsmhJNuGaebE4+qjhs/frbDUkyfsAa7xCqyR27UGH3dqWkyfxEpQJ6Ew6y?= =?us-ascii?Q?daY6AIN4n1ToUKvGQqHf/Dug0J2RKG/SS1lq/+k3FDAt2u7Tpp6LIr2rNffC?= =?us-ascii?Q?26eMsFvfGDVvFj1LA8ABWk8B6GMNGKuquKwdqmtzDfAZxx5M7LNQi67gxCbM?= =?us-ascii?Q?UFKCyLBdb3AQ+ul2C3ZMc+Qy/5ek1x7ysRHMH4UwOKWpLbEwjgAdor798Xz7?= =?us-ascii?Q?CE/sw7Ob6JRSIW0WCY8A4LjP3JUAyzd9o/ab2L5mMs4oOUE5HV9M7kpuFXWv?= =?us-ascii?Q?kouVQmtJll/x1YPhVuCliZbaZcEiFzqvlAi9s3GALsQV8/9BAgS90KyctjuM?= =?us-ascii?Q?vBbR0MPaFNocfPZCoSB9NsERcGpdQziYYIOFJZGrRqSOxe7IKYC1uY6N38Q4?= =?us-ascii?Q?B1f2JN4MQcFR7NTEnpZCqZwdqE+OeRq/GEkhQJ++lB3jq6gKjU53mRQduKuR?= =?us-ascii?Q?RBXk9XMK47cEjPkaKJcf2xcSJ7B9uMIVOnlx0O2I7OTcGdjGXzJsgG9e1A3U?= =?us-ascii?Q?7ld5lARvllFsHmvVJGskdCgCxmnUwlxLSehu?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jul 2025 07:14:02.2113 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6d921274-e6c3-4d9f-159e-08ddc8262b9a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001E8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5836 From: Lama Kayal The reservation size formula can be reduced to a simple evaluation of MLX5E_SHAMPO_WQ_RESRV_SIZE. This leaves mlx5e_shampo_get_log_rsrv_size() with one single use, which can be replaced with a macro for simplicity. Also, function mlx5e_shampo_get_log_rsrv_size() is used only throughout params.c, make it static. Signed-off-by: Lama Kayal Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan Reviewed-by: Michal Swiatkowski --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 5 +-- .../ethernet/mellanox/mlx5/core/en/params.c | 36 +++++++------------ .../ethernet/mellanox/mlx5/core/en/params.h | 4 --- 3 files changed, 16 insertions(+), 29 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h index b6340e9453c0..b25147442c92 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -85,8 +85,9 @@ struct page_pool; #define MLX5E_SHAMPO_WQ_HEADER_PER_PAGE (PAGE_SIZE >> MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE) #define MLX5E_SHAMPO_LOG_WQ_HEADER_PER_PAGE (PAGE_SHIFT - MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE) #define MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE (64) -#define MLX5E_SHAMPO_WQ_RESRV_SIZE (64 * 1024) -#define MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE (4096) +#define MLX5E_SHAMPO_WQ_RESRV_SIZE_BASE_SHIFT (12) +#define MLX5E_SHAMPO_WQ_LOG_RESRV_SIZE (16) +#define MLX5E_SHAMPO_WQ_RESRV_SIZE BIT(MLX5E_SHAMPO_WQ_LOG_RESRV_SIZE) #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \ (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c index fc945bce933a..86f6147de22b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c @@ -420,19 +420,10 @@ u8 mlx5e_shampo_get_log_hd_entry_size(struct mlx5_core_dev *mdev, return order_base_2(DIV_ROUND_UP(MLX5E_RX_MAX_HEAD, MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE)); } -u8 mlx5e_shampo_get_log_rsrv_size(struct mlx5_core_dev *mdev, - struct mlx5e_params *params) +static u8 mlx5e_shampo_get_log_pkt_per_rsrv(struct mlx5e_params *params) { - return order_base_2(MLX5E_SHAMPO_WQ_RESRV_SIZE / MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE); -} - -u8 mlx5e_shampo_get_log_pkt_per_rsrv(struct mlx5_core_dev *mdev, - struct mlx5e_params *params) -{ - u32 resrv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) * - MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE; - - return order_base_2(DIV_ROUND_UP(resrv_size, params->sw_mtu)); + return order_base_2(DIV_ROUND_UP(MLX5E_SHAMPO_WQ_RESRV_SIZE, + params->sw_mtu)); } u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev, @@ -834,13 +825,12 @@ static u32 mlx5e_shampo_get_log_cq_size(struct mlx5_core_dev *mdev, struct mlx5e_params *params, struct mlx5e_xsk_param *xsk) { - int rsrv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) * - MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE; u16 num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk)); - int pkt_per_rsrv = BIT(mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params)); u8 log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk); + int pkt_per_rsrv = BIT(mlx5e_shampo_get_log_pkt_per_rsrv(params)); int wq_size = BIT(mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk)); int wqe_size = BIT(log_stride_sz) * num_strides; + int rsrv_size = MLX5E_SHAMPO_WQ_RESRV_SIZE; /* +1 is for the case that the pkt_per_rsrv dont consume the reservation * so we get a filler cqe for the rest of the reservation. @@ -932,10 +922,11 @@ int mlx5e_build_rq_param(struct mlx5_core_dev *mdev, MLX5_SET(wq, wq, shampo_enable, true); MLX5_SET(wq, wq, log_reservation_size, - mlx5e_shampo_get_log_rsrv_size(mdev, params)); + MLX5E_SHAMPO_WQ_LOG_RESRV_SIZE - + MLX5E_SHAMPO_WQ_RESRV_SIZE_BASE_SHIFT); MLX5_SET(wq, wq, log_max_num_of_packets_per_reservation, - mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params)); + mlx5e_shampo_get_log_pkt_per_rsrv(params)); MLX5_SET(wq, wq, log_headers_entry_size, mlx5e_shampo_get_log_hd_entry_size(mdev, params)); lro_timeout = @@ -1048,18 +1039,17 @@ u32 mlx5e_shampo_hd_per_wqe(struct mlx5_core_dev *mdev, struct mlx5e_params *params, struct mlx5e_rq_param *rq_param) { - int resv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) * - MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE; u16 num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, NULL)); - int pkt_per_resv = BIT(mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params)); u8 log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL); + int pkt_per_rsrv = BIT(mlx5e_shampo_get_log_pkt_per_rsrv(params)); int wqe_size = BIT(log_stride_sz) * num_strides; + int rsrv_size = MLX5E_SHAMPO_WQ_RESRV_SIZE; u32 hd_per_wqe; /* Assumption: hd_per_wqe % 8 == 0. */ - hd_per_wqe = (wqe_size / resv_size) * pkt_per_resv; - mlx5_core_dbg(mdev, "%s hd_per_wqe = %d rsrv_size = %d wqe_size = %d pkt_per_resv = %d\n", - __func__, hd_per_wqe, resv_size, wqe_size, pkt_per_resv); + hd_per_wqe = (wqe_size / rsrv_size) * pkt_per_rsrv; + mlx5_core_dbg(mdev, "%s hd_per_wqe = %d rsrv_size = %d wqe_size = %d pkt_per_rsrv = %d\n", + __func__, hd_per_wqe, rsrv_size, wqe_size, pkt_per_rsrv); return hd_per_wqe; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.h b/drivers/net/ethernet/mellanox/mlx5/core/en/params.h index bd5877acc5b1..919895f64dcd 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.h @@ -97,10 +97,6 @@ u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5_core_dev *mdev, struct mlx5e_xsk_param *xsk); u8 mlx5e_shampo_get_log_hd_entry_size(struct mlx5_core_dev *mdev, struct mlx5e_params *params); -u8 mlx5e_shampo_get_log_rsrv_size(struct mlx5_core_dev *mdev, - struct mlx5e_params *params); -u8 mlx5e_shampo_get_log_pkt_per_rsrv(struct mlx5_core_dev *mdev, - struct mlx5e_params *params); u32 mlx5e_shampo_hd_per_wqe(struct mlx5_core_dev *mdev, struct mlx5e_params *params, struct mlx5e_rq_param *rq_param); -- 2.31.1