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Tue, 12 Aug 2025 07:17:57 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Richard Cochran" , , , , Gal Pressman , Thomas Gleixner , Carolina Jubran , Vladimir Oltean , "Dragos Tatulea" Subject: [PATCH net-next V2 0/3] Support exposing raw cycle counters in PTP and mlx5 Date: Tue, 12 Aug 2025 17:17:05 +0300 Message-ID: <1755008228-88881-1-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D7:EE_|DM6PR12MB4338:EE_ X-MS-Office365-Filtering-Correlation-Id: 315c6580-e992-4269-5948-08ddd9ab12ce X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?utf-8?B?NEhWdndBYVZEc1VsRWZCNk5Ldm55WENrVVUxdWQyNHBrZFFzTCtvWTBjdjVN?= =?utf-8?B?eU5ORlZySXdyYnZRWXpBZE42UXp5RzYwMnFyOHNwK09oa0lPdG04QmNKVEFz?= =?utf-8?B?ZncrcFRDY3NSc254czdXY3RZYUxjdXlzd2prS2tTWjhMSWpZNXVESGVVYnZP?= =?utf-8?B?eVgvRXROQXo0SW1KLzlqMnlTNU1iN1ltM2o5SU1aWTJTRzZnVklMWWE0TnFs?= =?utf-8?B?UjBXY1VlRnZLSWRKYi9NWi9sYUxCU05BL25BMzFlS3g5TWYzZkc3cldkRk1H?= =?utf-8?B?SHR6cUtDRFZaL3MzNTRmMTMwNkZuYXF4M0xxVmZoTXZmVjU2SHp0elZpQVd3?= =?utf-8?B?Z0xPTDZjVUhRUjRQNVY4SzY2bmg2NzlvYjUyeGtZWksxTHQ3L0pKMy9nU3NM?= =?utf-8?B?RURxdzN4RjlHbThsdmg5dE1WWXhNLzRwZSs4bytVRXI4YWtpeDBic1lWcmM2?= =?utf-8?B?ZlpPT0h5RnJKUjljWS9nSy9NN25LM1VRMlI1U0RLdFBmTWxSeHIyd1c3Umlz?= =?utf-8?B?akx5d1pDdkI2d01rZnJONitxeWVkQk40c2VzTW9tVjdhOTVTckJxOHJYSGRI?= =?utf-8?B?elY1eWlvRGNUUWl3bktyeThFZzhYcUNOd1M0dlIvb2FXUmlNNkhiYWRpTWxy?= =?utf-8?B?eHRscDJ4YVNVTGlHTDJBcFRoOUd1TGVXeUFucGNCWjB1YXMzY0kwdVhUSDZm?= =?utf-8?B?cTVCcTFqMmpXczNkTDQ3QXZ0b1pzNWp4ekdqUHZoSEpIcXh2U2U0bCtNZEkv?= =?utf-8?B?aVh1SXR1bFBjRU9tVlpCa2oxYlF5SzBNaUJGeXUvcmhob1Bic2hpL3hieTBP?= =?utf-8?B?bS9USlhYR1QzUENXYSt0Y3A2cjBueFZhNU9HOUx0eDBjZ3VCQmk2TzFmcis0?= =?utf-8?B?NTVJNUVocFdoTUVURVJBZHluTVhGelRWTXRnNHg5NitsaGEyWDNUOU1YWmlR?= =?utf-8?B?N0pGT1ZkcGwxejNTRVJ0V1ZzTGt1V09UNDZocFdoSk52TzhGL3BDVnhPUHJD?= =?utf-8?B?S3dtRnY0anVidzZ5bHNLWFp5eExTTU42cUZmR1d4QUpvRnl0QjA3S09HTjJr?= =?utf-8?B?YlVPKzZMYXBpZ29ZcVp2dHdYN3pWS2ZxOVNheFVRKytUTDkvL2tuK1BKWlZF?= =?utf-8?B?dTU0ZFFiaWlZUUZ0MnoxQ3VSU3VjTTE1SkExTmJuM2R5ZC9FNEpUZGFHSWI3?= =?utf-8?B?d1NWQVZkdDk0eWNVdy9iZTVBSUliVDhLZXJteEZES3FvcG54OW16YUkyb0tK?= =?utf-8?B?R3k2ZTZpWVVCbmdiOVZKaHdKOG9sZVkvN0ROc3UzN2xPWE00ODVkMXlMMm00?= =?utf-8?B?MDlYeGY4REtGcFZ5cHFMOGVaNU5qWWZWbEpYVWtkR0Y2Nm9EbmJZaW52Tkpz?= =?utf-8?B?eW5hMStZU1dlTkdyTnAxMkpaYS96VnVHOTBic0hjNnA1cmdRTGVwQUt3ajdV?= =?utf-8?B?VCtaazAwZnNNamJ5bEkwdmZWL3dHSU90ekZTeUs4TTQ5U2llcENSa1VOWnZB?= =?utf-8?B?WDh0UXlWR3gwR2NVR1NMUlUyTERkZGxTY1ZCRExYZXFrTHV1aDBIaUo4c25B?= =?utf-8?B?YktSb3lUbGNYVFo3VlN6dXhZS3cxd1JzZ3dIOTd4RWNEdUZTVG91aU1ENmhG?= =?utf-8?B?Skd3bURHS2JXcENLY2VJWTNtNFV3Z0dVd21KNFI2dVp4akYvTitib0UvVm0w?= =?utf-8?B?TzZ1MXJTMUxTSlNUSFRhUHdOdFpGYkpIeDZ5SGRXRTY5U0d0S29ZMk5pUHNv?= =?utf-8?B?dEZpLzZrUHBCYWptanRvZEdSaThZSTJJQ0VYWnBGVEFRNEdFaFFML1dWTEc0?= =?utf-8?B?YzBUWjR1MlNlUG1EMEhpK1U2cDV5WVd1QWt3ZGFDKyt1dE9VRytsdmxPUEZI?= =?utf-8?B?R2k5cGlaSGhTWDZvMEUvdFFIa1dXcUVhNVBTNWtVZ3VKRnRqWlVoYmdyOVlW?= =?utf-8?B?a3FDT214alVsbGM1cFpkLzI0a0lOWUxlZlFaZ3dCMFZ3N1BjVzRNU3FsU3Nv?= =?utf-8?B?a2RYMGFJWXh5RHNnUVRYZkdnR0YzWnNqWWhHSTE4L21MV1EwZ2Ewa3d1Z2do?= =?utf-8?B?MW4yN09PeTE1Z0FFTTh4a1pPVDlza2hMT3Z1UT09?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(36860700013)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Aug 2025 14:18:13.4462 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 315c6580-e992-4269-5948-08ddd9ab12ce X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D7.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4338 Hi, This series by Carolina adds support in ptp and usage in mlx5 for exposing the raw free-running cycle counter of PTP hardware clocks. This is V2. Find previous one here: https://lore.kernel.org/all/1752556533-39218-1-git-send-email-tariqt@nvidia.com/ Find detailed description by Carolina below [1]. Regards, Tariq V2: - Extend the cover letter with more motivation and use cases. [1] This patch series introduces support for exposing the raw free-running cycle counter of PTP hardware clocks. When the device is in free-running mode, it emits timestamps as raw cycle values instead of nanoseconds. These values may be passed directly to user space through: - fwctl: exposes internal device event records that include raw cycle-based timestamps. - DPDK: retrieves CQEs that contain raw cycle counters, which are passed to user space unmodified. To address this, the series introduces two new ioctl commands that allow userspace to query the device's raw cycle counter together with host time: - PTP_SYS_OFFSET_PRECISE_CYCLES - PTP_SYS_OFFSET_EXTENDED_CYCLES These commands work like their existing counterparts but return the device timestamp in cycle units instead of real-time nanoseconds. This allows user space to collect (cycle, time) pairs and build a mapping between the device’s free-running clock and host time. This can also be useful in the XDP fast path: if a driver inserts the raw cycle value into metadata instead of a real-time timestamp, it can avoid the overhead of converting cycles to time in the kernel. Then userspace can resolve the cycle-to-time mapping using this ioctl when needed. The ioctl enables user space to correlate those with host time, without requiring the PHC to be synchronized, so long as the drift remains stable during collection. Adds the new PTP ioctls and integrates support in ptp_ioctl(): - ptp: Add ioctl commands to expose raw cycle counter values Support for exposing raw cycles in mlx5: - net/mlx5: Extract MTCTR register read logic into helper function - net/mlx5: Support getcyclesx and getcrosscycles Carolina Jubran (3): ptp: Add ioctl commands to expose raw cycle counter values net/mlx5: Extract MTCTR register read logic into helper function net/mlx5: Support getcyclesx and getcrosscycles .../ethernet/mellanox/mlx5/core/lib/clock.c | 113 ++++++++++++++++-- drivers/ptp/ptp_chardev.c | 34 ++++-- include/uapi/linux/ptp_clock.h | 4 + 3 files changed, 130 insertions(+), 21 deletions(-) base-commit: bc4c0a48bdad7f225740b8e750fdc1da6d85e1eb -- 2.40.1