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Tue, 12 Aug 2025 07:18:02 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Richard Cochran" , , , , Gal Pressman , Thomas Gleixner , Carolina Jubran , Vladimir Oltean , "Dragos Tatulea" Subject: [PATCH net-next V2 1/3] ptp: Add ioctl commands to expose raw cycle counter values Date: Tue, 12 Aug 2025 17:17:06 +0300 Message-ID: <1755008228-88881-2-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1755008228-88881-1-git-send-email-tariqt@nvidia.com> References: <1755008228-88881-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D7:EE_|IA1PR12MB8494:EE_ X-MS-Office365-Filtering-Correlation-Id: b5f7c527-5c2f-44ed-ca7b-08ddd9ab14ff X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|7416014|36860700013|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?hvE/rMKONTT+ctct4hBuKZNach67PO7wSC63UYyI7K5mypU97oCWPFe85dxP?= =?us-ascii?Q?2BN+mkr6EEy0jEkTzH6groYLYYs3rX/pYknPIpCyLwyGzCce8PHcZLIaaRX/?= =?us-ascii?Q?q2Bh2LH43zfiSph+r66/npwazm8OxNCiu7var9qLOmq5UjleXp26gSRKVAKC?= =?us-ascii?Q?hNi9dnMASPQ8jP43BaZ3hWFQZPCw/mgkdDv8xS2G63ki5U0UqO0UqGcEFleM?= =?us-ascii?Q?Ldg7rRhnytDj3Pqh93VQFFi99scfecInRBqmZq5onKNy1jyA8l5Su2dEvjjH?= =?us-ascii?Q?5IiKdZGcJXimewr2UUxq0y9nxaC5JEO+NFvnwDb3jB16CbCiuUvXz0cIeoV9?= =?us-ascii?Q?qztJkFQvOaz9MF2uHXtU33NTbYFBuxQ6BtWKS7oFzJNWLpsrsnob8QgxvNf9?= =?us-ascii?Q?cVuso2fcGubSkx1LcC2MkiDuvZZNFcmmz88Y0cTmgIs478LeCaTLArLCLE14?= =?us-ascii?Q?YVKTPVQANUcdHo7MixQ8ryFu9+ww1u+z25nJh8uAYXvghevsWejO+p5VXO0w?= =?us-ascii?Q?YfjCQz7A1nrXy/sPr5j74srEE5OHGAjrInrqK9o4x9MLUWFebQi4f++7su6S?= =?us-ascii?Q?YbxLH4RFqKStuZjzS6cxwoNYrg+jbc4ppcmmAyiDOTT2iAQd63WXMLBcNFUS?= =?us-ascii?Q?qCXwRFmCZPj4kkBzj1H83udHy6Px7xoZ1IFPrrsTw6/OvADMyHoKSEltHN2I?= =?us-ascii?Q?RRtmTgiToCs4HziAnac+8iu3RdvedI1ysB2TxMXQSvmC+JMQ6w75y1+hrO7Q?= =?us-ascii?Q?F1QSixiJEhVLt0yRkHNc1+svGMMJx1Dwe5vdSNv8Z3SSX/xE8IavRP+WFL4E?= =?us-ascii?Q?+SZh5pgd9QViDvb98DRMLxLDWqciC7KqMo6VfAN6kAmTHA6KcrIA20vIIPQP?= =?us-ascii?Q?9VmXZd6dw+BSuURmqmCnZocmkNwCo0g53kbgP9ByyIS85Jkxh8VGWBuVtX9t?= =?us-ascii?Q?1G5rZkiH+TZ+sSA/HdZKQsvXuw1OPA+NHFbIw/DEb1N0PNDq09Mnbbq+CgZH?= =?us-ascii?Q?YEkmps36drLlilvnKQC/yfIWaXe6Pbu8OmNSQ8jYBkZd7+Sigo9RFCj7RLbv?= =?us-ascii?Q?myC6RfWJYweFeSzyC8Fo9XBAd7FHMEsU+VqsGvAiPPq/i9QoJcp0j9IFX8R7?= =?us-ascii?Q?X2XQS1aGjd/diqIKIIArX+JXjVNLC+1LHCFExYDuQh3ZoVXD+wKE1tbcPT3F?= =?us-ascii?Q?CL1wyg/8KmB7aHNN6htuvXxZcu3tnab1SFI1a42DIBD96I0DOugHV3q/iY/u?= =?us-ascii?Q?Bu3Lf9W33aV7YQd+w1e0C+FxBx4MLLo/tSKUQxzYG+Ow6z6nzDCiOG9DrT3T?= =?us-ascii?Q?tpncBMBfvLyjQegBxsolkaJ9hkQh15iohKpgU8YY5zEJP0EWd5vw4tdKJyuS?= =?us-ascii?Q?shAljBvohzVsDDgQM+fWPBM0GoReshkOaGHJ/rLSm8Qhsf30agTnxQfZ9j8W?= =?us-ascii?Q?HRFKKZo2MYxc4E+DqxveNgEucIzEYA6F+pi13/cfZhf5j7j2cFhyvF/KkXLf?= =?us-ascii?Q?ID12RtPn0cDoigjZrFb1fPX8VJypJmXzeYw/?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(7416014)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Aug 2025 14:18:17.1154 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b5f7c527-5c2f-44ed-ca7b-08ddd9ab14ff X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D7.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8494 From: Carolina Jubran Introduce two new ioctl commands, PTP_SYS_OFFSET_PRECISE_CYCLES and PTP_SYS_OFFSET_EXTENDED_CYCLES, to allow user space to access the raw free-running cycle counter from PTP devices. These ioctls are variants of the existing PRECISE and EXTENDED offset queries, but instead of returning device time in realtime, they return the raw cycle counter value. Signed-off-by: Carolina Jubran Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- drivers/ptp/ptp_chardev.c | 34 ++++++++++++++++++++++++++-------- include/uapi/linux/ptp_clock.h | 4 ++++ 2 files changed, 30 insertions(+), 8 deletions(-) diff --git a/drivers/ptp/ptp_chardev.c b/drivers/ptp/ptp_chardev.c index 4ca5a464a46a..e9719f365aab 100644 --- a/drivers/ptp/ptp_chardev.c +++ b/drivers/ptp/ptp_chardev.c @@ -285,17 +285,21 @@ static long ptp_enable_pps(struct ptp_clock *ptp, bool enable) return ops->enable(ops, &req, enable); } -static long ptp_sys_offset_precise(struct ptp_clock *ptp, void __user *arg) +typedef int (*ptp_crosststamp_fn)(struct ptp_clock_info *, + struct system_device_crosststamp *); + +static long ptp_sys_offset_precise(struct ptp_clock *ptp, void __user *arg, + ptp_crosststamp_fn crosststamp_fn) { struct ptp_sys_offset_precise precise_offset; struct system_device_crosststamp xtstamp; struct timespec64 ts; int err; - if (!ptp->info->getcrosststamp) + if (!crosststamp_fn) return -EOPNOTSUPP; - err = ptp->info->getcrosststamp(ptp->info, &xtstamp); + err = crosststamp_fn(ptp->info, &xtstamp); if (err) return err; @@ -313,12 +317,17 @@ static long ptp_sys_offset_precise(struct ptp_clock *ptp, void __user *arg) return copy_to_user(arg, &precise_offset, sizeof(precise_offset)) ? -EFAULT : 0; } -static long ptp_sys_offset_extended(struct ptp_clock *ptp, void __user *arg) +typedef int (*ptp_gettimex_fn)(struct ptp_clock_info *, + struct timespec64 *, + struct ptp_system_timestamp *); + +static long ptp_sys_offset_extended(struct ptp_clock *ptp, void __user *arg, + ptp_gettimex_fn gettimex_fn) { struct ptp_sys_offset_extended *extoff __free(kfree) = NULL; struct ptp_system_timestamp sts; - if (!ptp->info->gettimex64) + if (!gettimex_fn) return -EOPNOTSUPP; extoff = memdup_user(arg, sizeof(*extoff)); @@ -346,7 +355,7 @@ static long ptp_sys_offset_extended(struct ptp_clock *ptp, void __user *arg) struct timespec64 ts; int err; - err = ptp->info->gettimex64(ptp->info, &ts, &sts); + err = gettimex_fn(ptp->info, &ts, &sts); if (err) return err; @@ -497,11 +506,13 @@ long ptp_ioctl(struct posix_clock_context *pccontext, unsigned int cmd, case PTP_SYS_OFFSET_PRECISE: case PTP_SYS_OFFSET_PRECISE2: - return ptp_sys_offset_precise(ptp, argptr); + return ptp_sys_offset_precise(ptp, argptr, + ptp->info->getcrosststamp); case PTP_SYS_OFFSET_EXTENDED: case PTP_SYS_OFFSET_EXTENDED2: - return ptp_sys_offset_extended(ptp, argptr); + return ptp_sys_offset_extended(ptp, argptr, + ptp->info->gettimex64); case PTP_SYS_OFFSET: case PTP_SYS_OFFSET2: @@ -523,6 +534,13 @@ long ptp_ioctl(struct posix_clock_context *pccontext, unsigned int cmd, case PTP_MASK_EN_SINGLE: return ptp_mask_en_single(pccontext->private_clkdata, argptr); + case PTP_SYS_OFFSET_PRECISE_CYCLES: + return ptp_sys_offset_precise(ptp, argptr, + ptp->info->getcrosscycles); + + case PTP_SYS_OFFSET_EXTENDED_CYCLES: + return ptp_sys_offset_extended(ptp, argptr, + ptp->info->getcyclesx64); default: return -ENOTTY; } diff --git a/include/uapi/linux/ptp_clock.h b/include/uapi/linux/ptp_clock.h index 18eefa6d93d6..65f187b5f0d0 100644 --- a/include/uapi/linux/ptp_clock.h +++ b/include/uapi/linux/ptp_clock.h @@ -245,6 +245,10 @@ struct ptp_pin_desc { _IOWR(PTP_CLK_MAGIC, 18, struct ptp_sys_offset_extended) #define PTP_MASK_CLEAR_ALL _IO(PTP_CLK_MAGIC, 19) #define PTP_MASK_EN_SINGLE _IOW(PTP_CLK_MAGIC, 20, unsigned int) +#define PTP_SYS_OFFSET_PRECISE_CYCLES \ + _IOWR(PTP_CLK_MAGIC, 21, struct ptp_sys_offset_precise) +#define PTP_SYS_OFFSET_EXTENDED_CYCLES \ + _IOWR(PTP_CLK_MAGIC, 22, struct ptp_sys_offset_extended) struct ptp_extts_event { struct ptp_clock_time t; /* Time event occurred. */ -- 2.40.1