From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34CAA257452; Sun, 21 Sep 2025 16:53:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758473595; cv=none; b=OFcirRpuo+PPp1HF2PCVMYUfvo4Wh//WBmPZp+KaQpwTSzdxMavRXXBNtWVenRitsYw1BVQSJLswoqnPLjwoNYCB5NRlJNDkh4+oKxrn8ecn/nRRusOU2gu+JTUCYMJFGZzdEcGkXHGHG1BRB41EFeehrez0lXImO/iipefWDiE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758473595; c=relaxed/simple; bh=OmcqAy6h/ICDeDYAwPRkFiDSOLcTRi9vj0g9g+5IZ6s=; h=Content-Type:MIME-Version:In-Reply-To:References:Subject:From:Cc: To:Date:Message-ID; b=gbyi1/5uUVuJBsDKqiXSCVB2XYFLJulRXO4paPya2VcIZO6pkzpQRVPUyA4DHGkR2uMCILjC6OxuccI4LrXsJgm/WKIkjqVP+ZMKKRWxR6LLsvpekieoL1nbkn3bmZ6QDhoMhs6XRPiw1kRcBbqS9vbkyrt3yynvkC+Ipguc+8o= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GKc6gR3K; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GKc6gR3K" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A102AC4CEE7; Sun, 21 Sep 2025 16:53:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758473594; bh=OmcqAy6h/ICDeDYAwPRkFiDSOLcTRi9vj0g9g+5IZ6s=; h=In-Reply-To:References:Subject:From:Cc:To:Date:From; b=GKc6gR3KcSeCvEA+k+1FuykK6Icfz8SrdmL58SfGBXBWxCVlPrfgm2DmBoUmAhMF5 eGEcQLx4DJVGfPu0JNhCxAZMaqth7NjamyXpUDRdA+B+IvQSUb3nTGslgSwpWND4Jo Ph+GAnap95cL2c6v26NUV37mii01ivbbay3LcavM8QVFPPwP1keXi6HMZMca8k+G1S smDICQwe4cXSdIeJBsqpmmaF+tnyoxO9Esqa7sQkB7YlcKCKs4MftDc/B6L367MoBW EqNkXmtfVyWuLQxczQoozKtXCJLsmYbzIlZGw8fk+uEhw6a4x1HpmJtg9Q5Qv+alNz OJaiTaUHw6Ydg== Content-Type: text/plain; charset="utf-8" Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable In-Reply-To: <20250915151947.277983-3-laura.nao@collabora.com> References: <20250915151947.277983-1-laura.nao@collabora.com> <20250915151947.277983-3-laura.nao@collabora.com> Subject: Re: [PATCH v6 02/27] clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC From: Stephen Boyd Cc: guangjie.song@mediatek.com, wenst@chromium.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, kernel@collabora.com, Laura Nao , =?utf-8?q?N=C3=ADcolas?= F . R . A . Prado To: Laura Nao , angelogioacchino.delregno@collabora.com, conor+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, mturquette@baylibre.com, p.zabel@pengutronix.de, richardcochran@gmail.com, robh@kernel.org Date: Sun, 21 Sep 2025 09:53:13 -0700 Message-ID: <175847359329.4354.2697873457619753075@lazor> User-Agent: alot/0.11 Quoting Laura Nao (2025-09-15 08:19:22) > MT8196 uses a combination of set/clr registers to control the PLL > enable state, along with a FENC bit to check the preparation status. > Add new set of PLL clock operations with support for set/clr enable and > FENC status logic. >=20 > Reviewed-by: N=C3=ADcolas F. R. A. Prado > Reviewed-by: AngeloGioacchino Del Regno > Reviewed-by: Chen-Yu Tsai > Signed-off-by: Laura Nao > --- Applied to clk-next