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Thu, 30 Oct 2025 06:33:12 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , "Carolina Jubran" , Simon Horman Subject: [PATCH net-next V2 2/7] net/mlx5e: Use TIR API in mlx5e_modify_tirs_lb() Date: Thu, 30 Oct 2025 15:32:34 +0200 Message-ID: <1761831159-1013140-3-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1761831159-1013140-1-git-send-email-tariqt@nvidia.com> References: <1761831159-1013140-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044FB:EE_|SN7PR12MB8601:EE_ X-MS-Office365-Filtering-Correlation-Id: ffa6678d-3bd4-4658-7e80-08de17b8f00f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|7416014|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?fN8QOWb65N9hj3QWSF/rM6frwf7aONNwQHvWxQIABWSC4tTzHMnH7yskq3NN?= =?us-ascii?Q?M1HoRskNJeQabJQp/PWOoUJfL46BCY8R5DcM2n703r8ksWvwVNCGBj6u8DfV?= =?us-ascii?Q?8OWI53Iny6lClvqWEt2n0qDB/g6aL/W8SPveiZGuqei6/ds5ziZ6yo7p/9n7?= =?us-ascii?Q?IlsEg+TCpVLx5j42dLqYXbVH25xLQh5mlWWH/V4AEz0EI+VQhqV3NEts52xd?= =?us-ascii?Q?xwwxXNn0Oly4FlvvXMKnHyBVfa8TEbzo4kDaf9VxdlfXcEBMD0kzxA+0LbD+?= =?us-ascii?Q?XS+t7AHrSSdVrto2DPBW2Qft/FXKv2VXnyJuAJvDEo5oy1KPVuSu1N6Wa9Uz?= =?us-ascii?Q?fAeWAsr87/VsjG4dOEu077w0UXZ9f8YJ7tjrAcfYJfmq1iZCFJWfZpESVwyE?= =?us-ascii?Q?0RNP80hhw/6iHbjqQun3D+VHY44nFIErEdQuxCk2qEiaMd04dYjoSf1OX/b4?= =?us-ascii?Q?O5fleq4g1ew0Plrc/GOcfZn3T3z/DA8hB9JaS6f+JX6kPEWEqpQ2n9Rg3oyk?= =?us-ascii?Q?ZEJQDNZJx/xnHYR8hOxCCc7EfSqO3AYJCevI18KV4TLmK52cwkzPz3VkLar6?= =?us-ascii?Q?IhrIuLNOLQlPsb3BdRWlIsTxl4yM7GatS6+SNf5V0YkEqEzcw6lYuc+q+oxh?= =?us-ascii?Q?P5DvLBmDDjDSZwX7DiXg1mppoAq6CLZ1EnPQPweKSU3DMWzvZSNp6jGR9PG+?= =?us-ascii?Q?jEJEQW8wTZgQOZR7dUCSTFjmyuMvNfJitBccLn/cXGWNJxxwFZLRlReI2BuA?= =?us-ascii?Q?ABu0GbTGH60pTMZEjL/FVlfRhHVLaiTbZSOfnEhTE3mPm8e5y4qVUdYA4qq6?= =?us-ascii?Q?ZsQXgeT7oll60prZCyrBFAYaJdElIpiwmTTwDgvUr0aRVkE4wcdzRzyy3b4r?= =?us-ascii?Q?1Zv9iYDJurxzJFNVObNwCJ/bLyyRRt4Ts2JpM7Iwfj+xLEC/nXFIRa0lrKH6?= =?us-ascii?Q?5RTqzzZRFkysyo3yd4AL+V4VQaLl4qXcYH3pAjP8p0gk4q9CnMIUHOG0c2bx?= =?us-ascii?Q?buStnow15FIY4/kWo+zAhNswBIXLd1kS+n8wtdYkjNc+sPxZKntmcwQ6ifhi?= =?us-ascii?Q?zVSRhrsj/ah6gHzV6ROTGM6G9/OgUiTPNUyjZuGI9F0x7wj/g+PDbuHI+gV+?= =?us-ascii?Q?7oOVBSXr6vVMpGqZh4rQw2/F1zTX4M6/kJWZH9+///nU8KsGlelEl9fnaSbL?= =?us-ascii?Q?QwgFH8q5z7/YAsCQ6AainpjiNPuCtGfLJXsWeB9/lJ+1U/3j2VODzLg1gAXD?= =?us-ascii?Q?t+zUMts9y2ReMane8tA8Ra9gLBzhMFjWiffHURH4RVlKaGcmEJ/HrEgx4lf8?= =?us-ascii?Q?q3WPepUcPtBxYzoUplesUPYpPSf+vi9qgSEqajAxyoz7pEiY7EjU/O93Vc4c?= =?us-ascii?Q?CKxNj7aEoAPsNbuzf1Zj2jQmz/5JeTbTyp+oXBuwMh9QINjulzw7bPwZmNP/?= =?us-ascii?Q?Iy1qNqxTgI9qneU1osW8sDroOI4sGm/Pv9MO3PhdzcZRnHxK8F4QOg03kzYT?= =?us-ascii?Q?+MLYE0Qs/PI36Ja2tbg0Z2YAwnDaEc2e/YBDmSY3bjqvf/ejqSNLgO/RQ4V0?= =?us-ascii?Q?Ma1TZ13bYyd+3kVRpUM=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(7416014)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Oct 2025 13:33:40.1109 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ffa6678d-3bd4-4658-7e80-08de17b8f00f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FB.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8601 Extend the TIR API and use it in mlx5e_modify_tirs_lb() instead of the explicit modify_tir code. Signed-off-by: Tariq Toukan Reviewed-by: Carolina Jubran Reviewed-by: Dragos Tatulea --- .../net/ethernet/mellanox/mlx5/core/en/tir.c | 29 +++++++++++-- .../net/ethernet/mellanox/mlx5/core/en/tir.h | 3 ++ .../ethernet/mellanox/mlx5/core/en_common.c | 41 +++++++------------ 3 files changed, 43 insertions(+), 30 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tir.c b/drivers/net/ethernet/mellanox/mlx5/core/en/tir.c index 19499072f67f..0b55e77f19c8 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/tir.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tir.c @@ -146,6 +146,31 @@ void mlx5e_tir_builder_build_direct(struct mlx5e_tir_builder *builder) MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8); } +static void mlx5e_tir_context_self_lb_block(void *tirc, bool enable_uc_lb, + bool enable_mc_lb) +{ + u8 lb_flags = 0; + + if (enable_uc_lb) + lb_flags = MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; + if (enable_mc_lb) + lb_flags |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; + + MLX5_SET(tirc, tirc, self_lb_block, lb_flags); +} + +void mlx5e_tir_builder_build_self_lb_block(struct mlx5e_tir_builder *builder, + bool enable_uc_lb, + bool enable_mc_lb) +{ + void *tirc = mlx5e_tir_builder_get_tirc(builder); + + if (builder->modify) + MLX5_SET(modify_tir_in, builder->in, bitmask.self_lb_en, 1); + + mlx5e_tir_context_self_lb_block(tirc, enable_uc_lb, enable_mc_lb); +} + void mlx5e_tir_builder_build_tls(struct mlx5e_tir_builder *builder) { void *tirc = mlx5e_tir_builder_get_tirc(builder); @@ -153,9 +178,7 @@ void mlx5e_tir_builder_build_tls(struct mlx5e_tir_builder *builder) WARN_ON(builder->modify); MLX5_SET(tirc, tirc, tls_en, 1); - MLX5_SET(tirc, tirc, self_lb_block, - MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST | - MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST); + mlx5e_tir_context_self_lb_block(tirc, true, true); } int mlx5e_tir_init(struct mlx5e_tir *tir, struct mlx5e_tir_builder *builder, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tir.h b/drivers/net/ethernet/mellanox/mlx5/core/en/tir.h index e8df3aaf6562..958eeb959a19 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/tir.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tir.h @@ -35,6 +35,9 @@ void mlx5e_tir_builder_build_rss(struct mlx5e_tir_builder *builder, const struct mlx5e_rss_params_traffic_type *rss_tt, bool inner); void mlx5e_tir_builder_build_direct(struct mlx5e_tir_builder *builder); +void mlx5e_tir_builder_build_self_lb_block(struct mlx5e_tir_builder *builder, + bool enable_uc_lb, + bool enable_mc_lb); void mlx5e_tir_builder_build_tls(struct mlx5e_tir_builder *builder); struct mlx5_core_dev; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_common.c b/drivers/net/ethernet/mellanox/mlx5/core/en_common.c index 376a018b2db1..022a0cf7063c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_common.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_common.c @@ -250,44 +250,31 @@ void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev) int mlx5e_modify_tirs_lb(struct mlx5_core_dev *mdev, bool enable_uc_lb, bool enable_mc_lb) { + struct mlx5e_tir_builder *builder; struct mlx5e_tir *tir; - u8 lb_flags = 0; - int err = 0; - u32 tirn = 0; - int inlen; - void *in; + int err = 0; - inlen = MLX5_ST_SZ_BYTES(modify_tir_in); - in = kvzalloc(inlen, GFP_KERNEL); - if (!in) + builder = mlx5e_tir_builder_alloc(true); + if (!builder) return -ENOMEM; - if (enable_uc_lb) - lb_flags = MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; - - if (enable_mc_lb) - lb_flags |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; - - if (lb_flags) - MLX5_SET(modify_tir_in, in, ctx.self_lb_block, lb_flags); - - MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1); + mlx5e_tir_builder_build_self_lb_block(builder, enable_uc_lb, + enable_mc_lb); mutex_lock(&mdev->mlx5e_res.hw_objs.td.list_lock); list_for_each_entry(tir, &mdev->mlx5e_res.hw_objs.td.tirs_list, list) { - tirn = tir->tirn; - err = mlx5_core_modify_tir(mdev, tirn, in); - if (err) + err = mlx5e_tir_modify(tir, builder); + if (err) { + mlx5_core_err(mdev, + "modify tir(0x%x) enable_lb uc(%d) mc(%d) failed, %d\n", + mlx5e_tir_get_tirn(tir), + enable_uc_lb, enable_mc_lb, err); break; + } } mutex_unlock(&mdev->mlx5e_res.hw_objs.td.list_lock); - kvfree(in); - if (err) - mlx5_core_err(mdev, - "modify tir(0x%x) enable_lb uc(%d) mc(%d) failed, %d\n", - tirn, - enable_uc_lb, enable_mc_lb, err); + mlx5e_tir_builder_free(builder); return err; } -- 2.31.1