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Thu, 30 Oct 2025 06:33:40 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , "Carolina Jubran" , Simon Horman Subject: [PATCH net-next V2 7/7] net/mlx5e: Defer channels closure to reduce interface down time Date: Thu, 30 Oct 2025 15:32:39 +0200 Message-ID: <1761831159-1013140-8-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1761831159-1013140-1-git-send-email-tariqt@nvidia.com> References: <1761831159-1013140-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000015:EE_|PH7PR12MB7844:EE_ X-MS-Office365-Filtering-Correlation-Id: 43020b37-e1c9-4cc3-65f0-08de17b8ffe1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?brIwWtfSk5HW/H5GLWvlcWEBClpr9TG2aXbdJ0PcpKRUyyeLtngfgv/GZet4?= =?us-ascii?Q?lKbr1m1gAlwHh+JmBtBRF05U3JAy0+TbdNgsXtaYn/EFeAwoYdj5Gyp+Y0/h?= =?us-ascii?Q?Q4/hmcUsdShlbUhwEHzH1rCKsvpBTit6bvP23m7ve+8AYX6Qr77Z64fHYolD?= =?us-ascii?Q?N1plbIZD8qGQY5O2g7kh2JWZMhbwkt/B3HpUfdr50r1MDBDKYS5UyZmWDlY2?= =?us-ascii?Q?UbVHPAB/KAw3z4ERnn0qcL63/KDMra4Pgs0HJuqmcg44vzo136v3mcxXMsqC?= =?us-ascii?Q?PgL+km0je0UAejH769AMfDRLeBLckLrPPq73/f5dj77uLZ74Pp5lMx2aj+1+?= =?us-ascii?Q?AKtilDERGFdDoUWa5tM/Aflxef9AsQpeLYCw8CqkTUPoH8V0KZrykuO3Ahan?= =?us-ascii?Q?r15mtPi2rA9JVpiu6QkDfDz6XpW/iGkZ7dtP4w9HLHTfDuHU3Ik+LHWS8Rr3?= =?us-ascii?Q?iToinYIwSQL4qZw3Fp2hyO22WUwkRG4fQ9plE9mDNLd1IkhKd4Zd/zhzdppo?= =?us-ascii?Q?DP4t6swS/jXchSNIbHXK8YyY7FaA3SKc/YDUvuNkBg15hoJB8kNlJBpkg+jO?= =?us-ascii?Q?aGGsfiCcPWsjRxKUn7BZK2QvQ8XMeFxpM5pRGzs5HLaZ7+n71USVJNMfCUc6?= =?us-ascii?Q?a/hlJAB04gf0RYLdY6Pma7kRgr4tEe8C856ga0kJc7xQopMV1QzGuJd5V8wC?= =?us-ascii?Q?o+sfwYeHNfYmp4iVP+6oHXfEuligjzZ3XQwq+e6nCII0Qq7leh2Jhq4nv4Fe?= =?us-ascii?Q?rkhb8g0Jzb2s4Yv6f+4PfMkHuglQEph4i7CP2fQbVsnRTCOAymrlLRNlOkQH?= =?us-ascii?Q?1VxHZ3Z9DiVrCugexGoTJuyclS4WrFFiOY/4lRrGuTYnGNBklnBc+QBNxbwj?= =?us-ascii?Q?LDzHP8noGI8OSkYRNJIdGpkS+NybWS9Yxjj94b2yRHl40qHiytsNukWYANkn?= =?us-ascii?Q?AvtG94DqF6iD4cD7joTMhKsxPVo2GcQbw8OI+AIDy0GDdPT0Jiu6UFs7+Vfu?= =?us-ascii?Q?npvP6IRCmSYFetocTrBawSUfy5x+qn8zsB5JAjVANvI8ZqQ0LyUQ4JIowndR?= =?us-ascii?Q?/D2dF63HTN98Aq9sJiUn2a4BKmk1RW8DoIep7qoWK+6u3tLA22YU2gQGySo8?= =?us-ascii?Q?3fEjkr0G1NN8an2FGMcM7CQmdJPqrMv9jFWO0bE0bMRpp9Tn7cuO1t4DyBxM?= =?us-ascii?Q?Bb9R+tfncY9H6u5/2Ba+v3xRzGOMDp+e7ZhVgmQgHUNuhY+4PAKqXh9GPc0N?= =?us-ascii?Q?v9V23vaZLRLLDOMX7YBxPFzOw12jgbdRsOESW+XTfwX4ps1HYFbeTKptm7iC?= =?us-ascii?Q?0ljLuWsKLYaYcu8wMpemIO1twGGuWnXPbj7Y47XjWvuQToaFvCJNQC71cNuA?= =?us-ascii?Q?Ed/6K8sVCQ/ahzIXwWpEY//m3H/iMsxV0sXMI3/D15AA6tTw6KRh043BC+h8?= =?us-ascii?Q?1P6942nceWsW+10GegWnT8pd/hpbR48o5ByVR0KPPjSQ5oaNaFY0TsVSNovV?= =?us-ascii?Q?zVh5A9FKtVfHUw2u2LlqzhJLIJP6zcAeFVeijW9sQqGIYu4mIlZ1ztJlG0V4?= =?us-ascii?Q?QEtJIAGBQ6moA9jd/00=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Oct 2025 13:34:06.6054 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 43020b37-e1c9-4cc3-65f0-08de17b8ffe1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000015.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7844 Cap bit tis_tir_td_order=1 indicates that an old firmware requirement / limitation no longer exists. When unset, the latency of several firmware commands significantly increases with the presence of high number of co-existing channels (both old and new sets). Hence, we used to close unneeded old channels before invoking those firmware commands. Today, on capable devices, this is no longer the case. Minimize the interface down time by deferring the old channels closure, after the activation of the new ones. Perf numbers: Measured the number of dropped packets in a simple ping flood test, during a configuration change operation, that switches the number of channels from 247 to 248. Before: 71 packets lost After: 15 packets lost, ~80% saving. Signed-off-by: Tariq Toukan Reviewed-by: Carolina Jubran --- drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index 4edf64e1572a..9650fa6c6a63 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -3384,7 +3384,8 @@ static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv, } } - mlx5e_close_channels(old_chs); + if (!MLX5_CAP_GEN(priv->mdev, tis_tir_td_order)) + mlx5e_close_channels(old_chs); priv->profile->update_rx(priv); mlx5e_selq_apply(&priv->selq); @@ -3432,6 +3433,9 @@ int mlx5e_safe_switch_params(struct mlx5e_priv *priv, if (err) goto err_close; + if (MLX5_CAP_GEN(priv->mdev, tis_tir_td_order)) + mlx5e_close_channels(old_chs); + kfree(new_chs); kfree(old_chs); return 0; -- 2.31.1