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Mon, 12 Jan 2026 01:40:35 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Moshe Shemesh , Yevgeny Kliteynik Subject: [PATCH net-next 0/3] net/mlx5: HWS single flow counter support Date: Mon, 12 Jan 2026 11:40:22 +0200 Message-ID: <1768210825-1598472-1-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000143:EE_|DS2PR12MB9798:EE_ X-MS-Office365-Filtering-Correlation-Id: 08a8640b-de1c-442c-1684-08de51bead2b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?1haZ80cT0dwObDhaJJuZl4BvpqUOuHj0+EsaqSU9jNBAM1AUQdcwamnDcosX?= =?us-ascii?Q?n/4xRydlGorNY3pqo27hZaJgAvRgfhSEWisyYNaTV4lG/pjFHqhmZYV+7tFT?= =?us-ascii?Q?SzIqsELiiFt4uMkcnBChUodNDAEfpwzgpBhZIO/jZpi8QnJQoMe6X2VzpA4u?= =?us-ascii?Q?0I/KEioL7bT106TDBygtlOc3ixwxMgoDSsnMKhpJjjZ5Tl5+VxvwO3uhx21J?= =?us-ascii?Q?ldywOO3FIPvr70xFKbM0FMJHfyghHz9vnFQ3PwI5SvNImEO6oc0kOCTXHzEt?= =?us-ascii?Q?P/INnGiZqKy0LBbV6CB4jO2B/98ypuz+n6BtFbTlgbScMEswlgYAE+yE8PIe?= =?us-ascii?Q?gJsnrJQavhgSX+FkafFPIMtTmdMsdghK5988t4VwFYDlthfSKSKCVw23uSI0?= =?us-ascii?Q?1V0xcIBMq6AFIg99Z1E8eAG70cx3phiX7E6oGz/KmHqQ1HOdxjap24kgIzCF?= =?us-ascii?Q?5PLPIKJbTAnLdBxIb8uEOe2G1lYsEbVZrRrNwiwnfcOfp21SUYtSbUEmC+q3?= =?us-ascii?Q?EJmqtC+gxKlJpFbgnXaap12hOvm6Vu5/HuEzJYuieQtNNoa5silX2TUNrIug?= =?us-ascii?Q?ThLd7xPtpatME1FebA8rfXhV9vVAnS/fvntHeoFgSIa+FatkG2TPbMs2eckz?= =?us-ascii?Q?dznCwYGeWUvS/ahihFJsgOAN86hQsV/RzuxpVwK/aFQi8NsAnQ7oRWQRn9m5?= =?us-ascii?Q?Pwx4faHngDmbT5SCDpCbDKQbk9ZNfpIgGD7duTNJXoJmIv0gGHS/wUpDkpJG?= =?us-ascii?Q?9McPyCTDj/murNBTeG8h32q+bqpFXDfiWYyZ8+cjBCW7yzr8N9PASFVehdL6?= =?us-ascii?Q?bnQkeEwxEmEhiEAMSCA8Gf56fRgKtuz1inmOFvWRBx+4AJtJimXQM2j+7ZkW?= =?us-ascii?Q?PrnrNzvFIwJIJHLc+8NpdBaWxYyv1SMKhHQcIImWHSQh/LehLn7SYhyugHoq?= =?us-ascii?Q?OpVLs7OBEixF/+OCBWLcg1CkFTBhHitgK11/80/alBfTi5pV0SO0mXdfeCt1?= =?us-ascii?Q?JsPvk4T3feqPzJNOtLnMsvbb0quavgJAgp/gI3n/o24IOLJza1Q/vxNUXWuH?= =?us-ascii?Q?uQDrGIvcVnvssq1ffsWu0klzypY3gUMEcs1f8by5DEMOs2pVrIYldhipSOD/?= =?us-ascii?Q?sedUmNJxUOZKVycfcF/a0eQbgA1xEEJSpykt+8vmvxqYVHuPm9AU4dmk+ObT?= =?us-ascii?Q?iMh9okPs9MDtXo6ppOpuTTpNnDcC1a/HBHF78eOPOSL0dgyv2QOX77bfl3ZE?= =?us-ascii?Q?aH5TqIQT3AZHOW04U/IVwZV68tVLCXCFOEMvDXsdlF1tXE1U0hueOYlZ20/j?= =?us-ascii?Q?XQXxlE9cKueAr5kN1PXBQt2xLVaCFmwnXNA3u9K1uCy7CnvDYX92qWsrajMf?= =?us-ascii?Q?Bte4wvqBGABKYyY0U0Tg3dzhb6tWDqzhXok1aLLKD7J5Mi9F4wsGPkfJGSMM?= =?us-ascii?Q?a1/MVlzKzr8TpyN1axONN1RpYYNP1aXwVhg68M8UBvs+h1kTJKaec23tzo3a?= =?us-ascii?Q?WMHH11gsFnfCSckYnlmi35LCw8gWLuxsz6qN6roZmNSCYu2AVkR/rt6Mdg8W?= =?us-ascii?Q?KLr2I5dNZZbenQBXILI=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jan 2026 09:40:52.2386 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 08a8640b-de1c-442c-1684-08de51bead2b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000143.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS2PR12MB9798 Hi, This small series refactors the flow counter bulk initialization code and extends it so that single flow counters are also usable by hardware steering (HWS) rules. Patches 1-2 refactor the bulk init path: first by factoring out common flow counter bulk initialization into mlx5_fc_bulk_init(), then by splitting the bitmap allocation into mlx5_fs_bulk_bitmap_alloc(), with no functional changes. Patch 3 initializes bulk data for counters allocated via mlx5_fc_single_alloc(), so they can be safely used by HWS rules. Regards, Tariq Mark Bloch (2): net/mlx5: fs, factor out flow counter bulk init net/mlx5: fs, split bulk init Moshe Shemesh (1): net/mlx5: Initialize bulk for single flow counters .../net/ethernet/mellanox/mlx5/core/fs_core.h | 3 +- .../ethernet/mellanox/mlx5/core/fs_counters.c | 47 ++++++++++++++----- .../net/ethernet/mellanox/mlx5/core/fs_pool.c | 16 ++++--- .../net/ethernet/mellanox/mlx5/core/fs_pool.h | 5 +- .../mlx5/core/steering/hws/fs_hws_pools.c | 8 +++- 5 files changed, 55 insertions(+), 24 deletions(-) base-commit: 60d8484c4cec811f5ceb6550655df74490d1a165 -- 2.31.1