From: "Rob Herring (Arm)" <robh@kernel.org>
To: Prabhakar <prabhakar.csengg@gmail.com>
Cc: "Jakub Kicinski" <kuba@kernel.org>,
netdev@vger.kernel.org, "Magnus Damm" <magnus.damm@gmail.com>,
linux-renesas-soc@vger.kernel.org,
"Heiner Kallweit" <hkallweit1@gmail.com>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Biju Das" <biju.das.jz@bp.renesas.com>,
"Eric Dumazet" <edumazet@google.com>,
"David S. Miller" <davem@davemloft.net>,
"Geert Uytterhoeven" <geert+renesas@glider.be>,
"Clément Léger" <clement.leger@bootlin.com>,
linux-kernel@vger.kernel.org,
"Lad Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>,
"Andrew Lunn" <andrew+netdev@lunn.ch>,
devicetree@vger.kernel.org, "Paolo Abeni" <pabeni@redhat.com>,
"Fabrizio Castro" <fabrizio.castro.jz@renesas.com>,
"Conor Dooley" <conor+dt@kernel.org>,
"Russell King" <linux@armlinux.org.uk>
Subject: Re: [PATCH net-next v3 1/2] dt-bindings: net: pcs: renesas,rzn1-miic: Add phy_link property
Date: Thu, 15 Jan 2026 11:36:32 -0600 [thread overview]
Message-ID: <176849859188.929140.12375075368934726420.robh@kernel.org> (raw)
In-Reply-To: <20260112173555.1166714-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
On Mon, 12 Jan 2026 17:35:54 +0000, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add the renesas,miic-phy-link-active-low property to allow configuring
> the active level of phy_link status signals provided by the MIIC block.
>
> EtherPHY link-up and link-down status is required as a hardware IP
> feature independent of whether GMAC or ETHSW is used. With GMAC, link
> state is retrieved via MDC/MDIO and handled in software. In contrast,
> ETHSW exposes dedicated PHY_LINK pins that provide this information
> directly in hardware.
>
> These PHY_LINK signals are required not only for host-controlled traffic
> but also for switch-only forwarding paths where frames are exchanged
> between external nodes without CPU involvement. This is particularly
> important for redundancy protocols such as DLR (Device Level Ring),
> which depend on fast detection of link-down events caused by cable or
> port failures. Handling such events purely in software introduces
> latency, which is why ETHSW provides dedicated hardware PHY_LINK pins.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2->v3:
> - Updated commit message
> - Renamed DT property from renesas,miic-phylink-active-low to
> renesas,miic-phy-link-active-low.
>
> v1->v2:
> - Updated commit message to elaborate the necessity of PHY link signals.
> ---
> .../devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml | 7 +++++++
> 1 file changed, 7 insertions(+)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
next prev parent reply other threads:[~2026-01-15 17:36 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-12 17:35 [PATCH net-next v3 0/2] net: pcs: rzn1-miic: Support configurable PHY_LINK polarity Prabhakar
2026-01-12 17:35 ` [PATCH net-next v3 1/2] dt-bindings: net: pcs: renesas,rzn1-miic: Add phy_link property Prabhakar
2026-01-15 17:36 ` Rob Herring (Arm) [this message]
2026-01-12 17:35 ` [PATCH net-next v3 2/2] net: pcs: rzn1-miic: Add PHY_LINK active-level configuration support Prabhakar
2026-01-19 14:19 ` [PATCH net-next v3 0/2] net: pcs: rzn1-miic: Support configurable PHY_LINK polarity patchwork-bot+netdevbpf
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