[PATCH net 0/4] ENETC v4 hardware integration fixes

[PATCH net 0/4] ENETC v4 hardware integration fixes

[Claudiu Manoil]

ENETC v4 targeted fixes addressing SoC level integration issues
regarding AXI settings and register access width.

Claudiu Manoil (4):
  net: enetc: Remove SI/BDR cacheability AXI settings for ENETC v4
  net: enetc: Remove CBDR cacheability AXI settings for ENETC v4
  net: enetc: Convert 16-bit register writes to 32-bit for ENETC v4
  net: enetc: Convert 16-bit register reads to 32-bit for ENETC v4

 drivers/net/ethernet/freescale/enetc/enetc.c    | 11 +++++++----
 .../net/ethernet/freescale/enetc/enetc4_pf.c    |  6 +++---
 .../net/ethernet/freescale/enetc/enetc_cbdr.c   |  4 ----
 drivers/net/ethernet/freescale/enetc/enetc_hw.h | 17 ++++++++++++++---
 4 files changed, 24 insertions(+), 14 deletions(-)

-- 
2.34.1

[PATCH net 1/4] net: enetc: Remove SI/BDR cacheability AXI settings for ENETC v4

[Claudiu Manoil]

For ENETC v4 these settings are controlled by the global ENETC
message and buffer cache attribute registers (EnBCAR and EnMCAR),
from the IERB register block.

The hardcoded cacheability settings were inherited from LS1028A,
and should be removed from the ENETC v4 driver as they conflict
with the global IERB settings.

Fixes: 99100d0d9922 ("net: enetc: add preliminary support for i.MX95 ENETC PF")
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
---
 drivers/net/ethernet/freescale/enetc/enetc.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/freescale/enetc/enetc.c b/drivers/net/ethernet/freescale/enetc/enetc.c
index 53b26cece16a..e380a4f39855 100644
--- a/drivers/net/ethernet/freescale/enetc/enetc.c
+++ b/drivers/net/ethernet/freescale/enetc/enetc.c
@@ -2512,10 +2512,13 @@ int enetc_configure_si(struct enetc_ndev_priv *priv)
 	struct enetc_hw *hw = &si->hw;
 	int err;
 
-	/* set SI cache attributes */
-	enetc_wr(hw, ENETC_SICAR0,
-		 ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT);
-	enetc_wr(hw, ENETC_SICAR1, ENETC_SICAR_MSI);
+	if (is_enetc_rev1(si)) {
+		/* set SI cache attributes */
+		enetc_wr(hw, ENETC_SICAR0,
+			 ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT);
+		enetc_wr(hw, ENETC_SICAR1, ENETC_SICAR_MSI);
+	}
+
 	/* enable SI */
 	enetc_wr(hw, ENETC_SIMR, ENETC_SIMR_EN);
 
-- 
2.34.1

RE: [PATCH net 1/4] net: enetc: Remove SI/BDR cacheability AXI settings for ENETC v4

[Wei Fang]

> For ENETC v4 these settings are controlled by the global ENETC
> message and buffer cache attribute registers (EnBCAR and EnMCAR),
> from the IERB register block.
> 
> The hardcoded cacheability settings were inherited from LS1028A,
> and should be removed from the ENETC v4 driver as they conflict
> with the global IERB settings.
> 
> Fixes: 99100d0d9922 ("net: enetc: add preliminary support for i.MX95 ENETC
> PF")
> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>

Reviewed-by: Wei Fang <wei.fang@nxp.com>

[PATCH net 2/4] net: enetc: Remove CBDR cacheability AXI settings for ENETC v4

[Claudiu Manoil]

For ENETC v4 these settings are controlled by the global ENETC
command cache attribute registers (EnCAR), from the IERB register
block.

The hardcoded CDBR cacheability settings were inherited from LS1028A,
and should be removed from the ENETC v4 driver as they conflict
with the global IERB settings.

Fixes: e3f4a0a8ddb4 ("net: enetc: add command BD ring support for i.MX95 ENETC")
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
---
 drivers/net/ethernet/freescale/enetc/enetc_cbdr.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/net/ethernet/freescale/enetc/enetc_cbdr.c b/drivers/net/ethernet/freescale/enetc/enetc_cbdr.c
index 3d5f31879d5c..a635bfdc30af 100644
--- a/drivers/net/ethernet/freescale/enetc/enetc_cbdr.c
+++ b/drivers/net/ethernet/freescale/enetc/enetc_cbdr.c
@@ -74,10 +74,6 @@ int enetc4_setup_cbdr(struct enetc_si *si)
 	if (!user->ring)
 		return -ENOMEM;
 
-	/* set CBDR cache attributes */
-	enetc_wr(hw, ENETC_SICAR2,
-		 ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT);
-
 	regs.pir = hw->reg + ENETC_SICBDRPIR;
 	regs.cir = hw->reg + ENETC_SICBDRCIR;
 	regs.mr = hw->reg + ENETC_SICBDRMR;
-- 
2.34.1

RE: [PATCH net 2/4] net: enetc: Remove CBDR cacheability AXI settings for ENETC v4

[Wei Fang]

> For ENETC v4 these settings are controlled by the global ENETC
> command cache attribute registers (EnCAR), from the IERB register
> block.
> 
> The hardcoded CDBR cacheability settings were inherited from LS1028A,
> and should be removed from the ENETC v4 driver as they conflict
> with the global IERB settings.
> 
> Fixes: e3f4a0a8ddb4 ("net: enetc: add command BD ring support for i.MX95
> ENETC")
> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
> ---
>  drivers/net/ethernet/freescale/enetc/enetc_cbdr.c | 4 ----
>  1 file changed, 4 deletions(-)
> 
> diff --git a/drivers/net/ethernet/freescale/enetc/enetc_cbdr.c
> b/drivers/net/ethernet/freescale/enetc/enetc_cbdr.c
> index 3d5f31879d5c..a635bfdc30af 100644
> --- a/drivers/net/ethernet/freescale/enetc/enetc_cbdr.c
> +++ b/drivers/net/ethernet/freescale/enetc/enetc_cbdr.c
> @@ -74,10 +74,6 @@ int enetc4_setup_cbdr(struct enetc_si *si)
>  	if (!user->ring)
>  		return -ENOMEM;
> 
> -	/* set CBDR cache attributes */
> -	enetc_wr(hw, ENETC_SICAR2,
> -		 ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT);
> -
>  	regs.pir = hw->reg + ENETC_SICBDRPIR;
>  	regs.cir = hw->reg + ENETC_SICBDRCIR;
>  	regs.mr = hw->reg + ENETC_SICBDRMR;
> --
> 2.34.1

Reviewed-by: Wei Fang <wei.fang@nxp.com>

[PATCH net 3/4] net: enetc: Convert 16-bit register writes to 32-bit for ENETC v4

[Claudiu Manoil]

For ENETC v4, which is integrated into more complex SoCs (compared to v1),
16‑bit register writes are blocked in the SoC interconnect on some chips.

To be fair, it is not recommended to access 32‑bit registers of this IP
using lower‑width accessors (i.e. 16‑bit), and the only exception to
this rule was introduced by me in the initial ENETC v1 driver for the
PMAR1 register, which holds the lower 16 bits of the primary MAC address
of an SI. Meanwhile, this exception has been replicated for v4 as well.

Since LS1028 (the only SoC with ENETC v1) is not affected by this issue,
the current patch fixes the 16‑bit writes to PMAR1 starting with ENETC
v4.

Fixes: 99100d0d9922 ("net: enetc: add preliminary support for i.MX95 ENETC PF")
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
---
 drivers/net/ethernet/freescale/enetc/enetc4_pf.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/freescale/enetc/enetc4_pf.c b/drivers/net/ethernet/freescale/enetc/enetc4_pf.c
index 498346dd996a..c0859d200a2c 100644
--- a/drivers/net/ethernet/freescale/enetc/enetc4_pf.c
+++ b/drivers/net/ethernet/freescale/enetc/enetc4_pf.c
@@ -59,10 +59,10 @@ static void enetc4_pf_set_si_primary_mac(struct enetc_hw *hw, int si,
 
 	if (si != 0) {
 		__raw_writel(upper, hw->port + ENETC4_PSIPMAR0(si));
-		__raw_writew(lower, hw->port + ENETC4_PSIPMAR1(si));
+		__raw_writel(lower, hw->port + ENETC4_PSIPMAR1(si));
 	} else {
 		__raw_writel(upper, hw->port + ENETC4_PMAR0);
-		__raw_writew(lower, hw->port + ENETC4_PMAR1);
+		__raw_writel(lower, hw->port + ENETC4_PMAR1);
 	}
 }
 
-- 
2.34.1

RE: [PATCH net 3/4] net: enetc: Convert 16-bit register writes to 32-bit for ENETC v4

[Wei Fang]

> For ENETC v4, which is integrated into more complex SoCs (compared to v1),
> 16‑bit register writes are blocked in the SoC interconnect on some chips.
> 
> To be fair, it is not recommended to access 32‑bit registers of this IP
> using lower‑width accessors (i.e. 16‑bit), and the only exception to
> this rule was introduced by me in the initial ENETC v1 driver for the
> PMAR1 register, which holds the lower 16 bits of the primary MAC address
> of an SI. Meanwhile, this exception has been replicated for v4 as well.
> 
> Since LS1028 (the only SoC with ENETC v1) is not affected by this issue,
> the current patch fixes the 16‑bit writes to PMAR1 starting with ENETC
> v4.
> 
> Fixes: 99100d0d9922 ("net: enetc: add preliminary support for i.MX95 ENETC
> PF")
> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
> ---
>  drivers/net/ethernet/freescale/enetc/enetc4_pf.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/net/ethernet/freescale/enetc/enetc4_pf.c
> b/drivers/net/ethernet/freescale/enetc/enetc4_pf.c
> index 498346dd996a..c0859d200a2c 100644
> --- a/drivers/net/ethernet/freescale/enetc/enetc4_pf.c
> +++ b/drivers/net/ethernet/freescale/enetc/enetc4_pf.c
> @@ -59,10 +59,10 @@ static void enetc4_pf_set_si_primary_mac(struct
> enetc_hw *hw, int si,
> 
>  	if (si != 0) {
>  		__raw_writel(upper, hw->port + ENETC4_PSIPMAR0(si));
> -		__raw_writew(lower, hw->port + ENETC4_PSIPMAR1(si));
> +		__raw_writel(lower, hw->port + ENETC4_PSIPMAR1(si));
>  	} else {
>  		__raw_writel(upper, hw->port + ENETC4_PMAR0);
> -		__raw_writew(lower, hw->port + ENETC4_PMAR1);
> +		__raw_writel(lower, hw->port + ENETC4_PMAR1);
>  	}
>  }
> 
> --
> 2.34.1

Reviewed-by: Wei Fang <wei.fang@nxp.com>

[PATCH net 4/4] net: enetc: Convert 16-bit register reads to 32-bit for ENETC v4

[Claudiu Manoil]

It is not recommended to access the 32‑bit registers of this hardware IP
using lower‑width accessors (i.e. 16‑bit), and the only exception to
this rule was introduced in the initial ENETC v1 driver for the PMAR1
register, which holds the lower 16 bits of the primary MAC address of
an SI. Meanwhile, this exception has been replicated in the v4 driver
code as well.

Since LS1028 (the only SoC with ENETC v1) is not affected by this issue,
the current patch converts the 16‑bit reads from PMAR1 starting with
ENETC v4.

Fixes: 99100d0d9922 ("net: enetc: add preliminary support for i.MX95 ENETC PF")
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
---
 .../net/ethernet/freescale/enetc/enetc4_pf.c    |  2 +-
 drivers/net/ethernet/freescale/enetc/enetc_hw.h | 17 ++++++++++++++---
 2 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/freescale/enetc/enetc4_pf.c b/drivers/net/ethernet/freescale/enetc/enetc4_pf.c
index c0859d200a2c..5850540634b0 100644
--- a/drivers/net/ethernet/freescale/enetc/enetc4_pf.c
+++ b/drivers/net/ethernet/freescale/enetc/enetc4_pf.c
@@ -73,7 +73,7 @@ static void enetc4_pf_get_si_primary_mac(struct enetc_hw *hw, int si,
 	u16 lower;
 
 	upper = __raw_readl(hw->port + ENETC4_PSIPMAR0(si));
-	lower = __raw_readw(hw->port + ENETC4_PSIPMAR1(si));
+	lower = __raw_readl(hw->port + ENETC4_PSIPMAR1(si));
 
 	put_unaligned_le32(upper, addr);
 	put_unaligned_le16(lower, addr + 4);
diff --git a/drivers/net/ethernet/freescale/enetc/enetc_hw.h b/drivers/net/ethernet/freescale/enetc/enetc_hw.h
index 7b882b8921fe..662e4fbafb74 100644
--- a/drivers/net/ethernet/freescale/enetc/enetc_hw.h
+++ b/drivers/net/ethernet/freescale/enetc/enetc_hw.h
@@ -708,13 +708,24 @@ struct enetc_cmd_rfse {
 #define ENETC_RFSE_EN	BIT(15)
 #define ENETC_RFSE_MODE_BD	2
 
+static inline void enetc_get_primary_mac_addr(struct enetc_hw *hw, u8 *addr)
+{
+	u32 upper;
+	u16 lower;
+
+	upper = __raw_readl(hw->reg + ENETC_SIPMAR0);
+	lower = __raw_readl(hw->reg + ENETC_SIPMAR1);
+
+	put_unaligned_le32(upper, addr);
+	put_unaligned_le16(lower, addr + 4);
+}
+
 static inline void enetc_load_primary_mac_addr(struct enetc_hw *hw,
 					       struct net_device *ndev)
 {
-	u8 addr[ETH_ALEN] __aligned(4);
+	u8 addr[ETH_ALEN];
 
-	*(u32 *)addr = __raw_readl(hw->reg + ENETC_SIPMAR0);
-	*(u16 *)(addr + 4) = __raw_readw(hw->reg + ENETC_SIPMAR1);
+	enetc_get_primary_mac_addr(hw, addr);
 	eth_hw_addr_set(ndev, addr);
 }
 
-- 
2.34.1

RE: [PATCH net 4/4] net: enetc: Convert 16-bit register reads to 32-bit for ENETC v4

[Wei Fang]

> It is not recommended to access the 32‑bit registers of this hardware IP
> using lower‑width accessors (i.e. 16‑bit), and the only exception to
> this rule was introduced in the initial ENETC v1 driver for the PMAR1
> register, which holds the lower 16 bits of the primary MAC address of
> an SI. Meanwhile, this exception has been replicated in the v4 driver
> code as well.
> 
> Since LS1028 (the only SoC with ENETC v1) is not affected by this issue,
> the current patch converts the 16‑bit reads from PMAR1 starting with
> ENETC v4.
> 
> Fixes: 99100d0d9922 ("net: enetc: add preliminary support for i.MX95 ENETC
> PF")
> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>

Reviewed-by: Wei Fang <wei.fang@nxp.com>

Re: [PATCH net 0/4] ENETC v4 hardware integration fixes

[patchwork-bot+netdevbpf]

Hello:

This series was applied to netdev/net.git (main)
by Jakub Kicinski <kuba@kernel.org>:

On Fri, 30 Jan 2026 16:10:31 +0200 you wrote:
> ENETC v4 targeted fixes addressing SoC level integration issues
> regarding AXI settings and register access width.
> 
> Claudiu Manoil (4):
>   net: enetc: Remove SI/BDR cacheability AXI settings for ENETC v4
>   net: enetc: Remove CBDR cacheability AXI settings for ENETC v4
>   net: enetc: Convert 16-bit register writes to 32-bit for ENETC v4
>   net: enetc: Convert 16-bit register reads to 32-bit for ENETC v4
> 
> [...]

Here is the summary with links:
  - [net,1/4] net: enetc: Remove SI/BDR cacheability AXI settings for ENETC v4
    https://git.kernel.org/netdev/net/c/a69c17230cab
  - [net,2/4] net: enetc: Remove CBDR cacheability AXI settings for ENETC v4
    https://git.kernel.org/netdev/net/c/9ae13b2e64fc
  - [net,3/4] net: enetc: Convert 16-bit register writes to 32-bit for ENETC v4
    https://git.kernel.org/netdev/net/c/21d0fc95b592
  - [net,4/4] net: enetc: Convert 16-bit register reads to 32-bit for ENETC v4
    https://git.kernel.org/netdev/net/c/c28d765ec5da

You are awesome, thank you!
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