From: patchwork-bot+netdevbpf@kernel.org
To: Daniel Machon <daniel.machon@microchip.com>
Cc: andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com,
kuba@kernel.org, pabeni@redhat.com, Steen.Hegelund@microchip.com,
UNGLinuxDriver@microchip.com, netdev@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH net] net: sparx5/lan969x: fix DWRR cost max to match hardware register width
Date: Fri, 13 Feb 2026 03:10:09 +0000 [thread overview]
Message-ID: <177095220983.1827286.14396517672847717184.git-patchwork-notify@kernel.org> (raw)
In-Reply-To: <20260210-sparx5-fix-dwrr-cost-max-v1-1-58fbdbc25652@microchip.com>
Hello:
This patch was applied to netdev/net.git (main)
by Jakub Kicinski <kuba@kernel.org>:
On Tue, 10 Feb 2026 14:44:01 +0100 you wrote:
> DWRR (Deficit Weighted Round Robin) scheduling distributes bandwidth
> across traffic classes based on per-queue cost values, where lower cost
> means higher bandwidth share.
>
> The SPX5_DWRR_COST_MAX constant is 63 (6 bits) but the hardware
> register field HSCH_DWRR_ENTRY_DWRR_COST is GENMASK(24, 20), only
> 5 bits wide (max 31). This causes sparx5_weight_to_hw_cost() to
> compute cost values that silently overflow via FIELD_PREP, resulting
> in incorrect scheduling weights.
>
> [...]
Here is the summary with links:
- [net] net: sparx5/lan969x: fix DWRR cost max to match hardware register width
https://git.kernel.org/netdev/net/c/6c28aa8dfdf2
You are awesome, thank you!
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prev parent reply other threads:[~2026-02-13 3:10 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-10 13:44 [PATCH net] net: sparx5/lan969x: fix DWRR cost max to match hardware register width Daniel Machon
2026-02-12 17:53 ` Simon Horman
2026-02-13 3:10 ` patchwork-bot+netdevbpf [this message]
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