From: patchwork-bot+netdevbpf@kernel.org
To: Raju Rangoju <Raju.Rangoju@amd.com>
Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
pabeni@redhat.com, kuba@kernel.org, edumazet@google.com,
davem@davemloft.net, andrew+netdev@lunn.ch,
Guruvendra.Punugupati@amd.com
Subject: Re: [PATCH net] amd-xgbe: fix MAC_TCR_SS register width for 2.5G and 10M speeds
Date: Sat, 28 Feb 2026 22:30:05 +0000 [thread overview]
Message-ID: <177231780505.3147597.8625597502733570293.git-patchwork-notify@kernel.org> (raw)
In-Reply-To: <20260226170753.250312-1-Raju.Rangoju@amd.com>
Hello:
This patch was applied to netdev/net.git (main)
by Jakub Kicinski <kuba@kernel.org>:
On Thu, 26 Feb 2026 22:37:53 +0530 you wrote:
> Extend the MAC_TCR_SS (Speed Select) register field width from 2 bits
> to 3 bits to properly support all speed settings.
>
> The MAC_TCR register's SS field encoding requires 3 bits to represent
> all supported speeds:
> - 0x00: 10Gbps (XGMII)
> - 0x02: 2.5Gbps (GMII) / 100Mbps
> - 0x03: 1Gbps / 10Mbps
> - 0x06: 2.5Gbps (XGMII) - P100a only
>
> [...]
Here is the summary with links:
- [net] amd-xgbe: fix MAC_TCR_SS register width for 2.5G and 10M speeds
https://git.kernel.org/netdev/net/c/9439a661c2e8
You are awesome, thank you!
--
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prev parent reply other threads:[~2026-02-28 22:30 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-26 17:07 [PATCH net] amd-xgbe: fix MAC_TCR_SS register width for 2.5G and 10M speeds Raju Rangoju
2026-02-28 22:30 ` patchwork-bot+netdevbpf [this message]
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