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Thu, 12 Mar 2026 13:07:12 -0700 (PDT) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Subject: Re: [PATCH v6 15/18] clk: mediatek: Add MT8189 dispsys clock support From: David Lechner To: "irving.ch.lin" Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Richard Cochran , Bartosz Golaszewski , Chen-Yu Tsai , Miles Chen , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Qiqi Wang , sirius.wang@mediatek.com, vince-wl.liu@mediatek.com, jh.hsu@mediatek.com In-Reply-To: <20260309120512.3624804-16-irving-ch.lin@mediatek.com> References: <20260309120512.3624804-1-irving-ch.lin@mediatek.com> <20260309120512.3624804-16-irving-ch.lin@mediatek.com> Date: Thu, 12 Mar 2026 15:06:36 -0500 Message-Id: <177334599652.4124794.12067751220383417571@freyr> X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=622; i=dlechner@baylibre.com; h=from:subject:message-id; bh=CMNpkQG0OX1ZmIY4eNoRhc5pN1fKRttQ1DPPmQGZ5Ok=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBpsxzklpGpUf/ZQQIyqz1DGbRxkAj3JX3gj9Fst kHYKcWEcLiJATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCabMc5AAKCRDCzCAB/wGP wAB9B/0amsj5mtHGl7JwYJ4m/8bCDd5vMrY9EYIYFmV67HC/3VsGnfj1wPsBIVVvEBbRl+IhIIA ZsVi+f/fEjvU6prplQZ/YZd8np1yTT1IWdeKgbGDDKpmhj+ay9gbv30oTZ7hntcUeH8jUMJrP/q tZU8uftAxgDKfME+lIWGswpoBwlUSOzobxeouycG+WNAHOkJA6P9MGeEtvRIK+FKpHbvhe8km04 Ox8e94DXUVshX9UMS9lDnF5G0nMYaWHn1RibGjXUQ/s0dnAAbbdC5p20fdx+NRF7/D6TTyYAO4N AauC6vpKcGuJ+POQeLop+wx9WdMiq97CgGUQthHxIRLRvwFx X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 On Mon, 09 Mar 2026 20:04:57 +0800, irving.ch.lin wrote: > Add support for the MT8189 dispsys clock controller, > which provides clock gate control for display system. > ... > + GATE_MM0(CLK_MMSYS_0_DISP_DVO, "mmsys_0_disp_dvo", "disp0_sel", 20), > + GATE_MM0(CLK_MMSYS_0_DISP_DSI0, "mmsys_0_CLK0", "disp0_sel", 21), Why the random CAPS here? Seems like the name should be "mmsys_0_disp_dsi0" instead of "mmsys_0_CLK0". > + /* MM1 */ > + GATE_MM1(CLK_MMSYS_1_DISP_DSI0, "mmsys_1_CLK0", "dsi_occ_sel", 0), Similar case here. -- David Lechner