Re: [PATCH rdma-next 11/23] RDMA/mlx5: Add shadow FIFO infrastructure for UMR completions

[netdev-bot+sashiko@kernel.org]

Thank you for your contribution! Sashiko AI review found more severe
issue(s) in other patches of this series. This mail is only an FYI, in case
you want to address the nit picks below when you respin.

Low priority / nit picks for your consideration:

- [Low] The commit message's design premise is wrong.

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RDMA/mlx5: Add shadow FIFO infrastructure for UMR completions

This commit adds a shadow FIFO of posted UMR contexts in adversarial
mode. A later patch can then check each UMR CQE against the oldest
pending request instead of trusting the CQE wqe_counter. Each context
also records the SQ producer counter it was posted at.

> The UMR QP is RC and signals every WR, so its completions arrive in
> posting order.

[Severity: Low]
Is this description accurate? The UMR QP does not look like an RC QP.

mlx5r_umr_resource_init() in drivers/infiniband/hw/mlx5/umr.c creates it
as a REG_UMR QP:

drivers/infiniband/hw/mlx5/umr.c:mlx5r_umr_resource_init() {
    ...
	init_attr.qp_type = MLX5_IB_QPT_REG_UMR;
    ...
}

to_mlx5_st() in drivers/infiniband/hw/mlx5/qp.c maps that type to its
own service type, not MLX5_QP_ST_RC:

	case MLX5_IB_QPT_REG_UMR:	return MLX5_QP_ST_REG_UMR;

mlx5r_umr_qp_rst2rts() also moves the QP to RTS without a remote QPN or
a path, which an RC connection would need.

The shadow FIFO design depends on in-order completion. The consumer added
later in the series, mlx5_ib_poll_one_umr(), treats any CQE whose
wqe_counter differs from the FIFO head as forged.

The in-order conclusion is probably still correct, since mlx5 send queues
complete in order and the generic poll path already relies on that when
it sets wq->tail = wq->wqe_head[idx] + 1. Only the stated reason seems
wrong.

Could the message say that the UMR SQ (a REG_UMR service type QP)
completes in posting order, instead of calling the QP RC?

-- 
Sashiko AI review · https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20261103163949.1554-1-yishaih%40nvidia.com