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[82.67.6.57]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a00cfae123sm101113665e9.13.2026.09.29.10.15.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Sep 2026 10:15:33 -0700 (PDT) From: Jerome Brunet To: Andrew Lunn Cc: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Richard Cochran , Maxime Ripard , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Maxime Chevallier , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Andre Przywara Subject: Re: [PATCH net-next v3 0/5] net: stmmac: Add support for Allwinner A733 GMAC210 In-Reply-To: <93870bce-b18e-4eed-a9ca-1d01313c61a7@lunn.ch> References: <20260923-allwinner-a733-gmac-support-v3-0-15735155a789@baylibre.com> <9cc61625-47c9-4bdf-97f0-0528f661a399@lunn.ch> <1j7bkb9h5k.fsf@starbuckisacylon.baylibre.com> <5fae3b42-552a-458a-9710-927360e58c37@lunn.ch> <1jv77u8yak.fsf@starbuckisacylon.baylibre.com> <491f043e-6dc6-4936-a490-31a3362c5b6e@lunn.ch> <1jse2x91oh.fsf@starbuckisacylon.baylibre.com> <1jecec3xnd.fsf@starbuckisacylon.baylibre.com> <93870bce-b18e-4eed-a9ca-1d01313c61a7@lunn.ch> Date: Tue, 29 Sep 2026 19:15:32 +0200 Message-ID: <1ja4p03rnv.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On mar. 29 sept. 2026 at 18:10, Andrew Lunn wrote: >> Thanks for the heads up. So if I'm reading the doc correctly the PHY >> adds 2ns >> * on RX if there a 4.7k pull-up on RXD0 >> * on TX if there a 4.7k pull-up on RXD1 >> >> The schematics for the board are available here [1] >> >> * 4.7k pull-up on RXD0: so we should have 2ns Rx from the PHY >> * 4.7k pull-down on RXD1: no idea what this does. Presumably no delay ? >> >> I've cross-checked the HW, the resistors are actually fitted as the >> schematic says they are. >> >> With the HW setup, the MAC setup that works for me remains >> >> tx-internal-delay-ps = <1620>; >> rx-internal-delay-ps = <1800>; > > These values suggests there are delays on both Rx an Tx. I did not mean to suggest :) To be clear, we have no control over the PHY delay. The strapping/doc says the PHY provide 2ns on Rx, none on Tx (presumably) But I must add 1.62ns on Tx and 1.8ns on Rx through the MAC for the link to work properly (the values above). I don't have an explanation for this. I assume the PHY actually adds no delay, maybe the strapping implementation is broken. Maybe the PCB the already adds a little delay which is why the MAC just need to add a little less than 2ns. > >> >> I know it is not aligned with what it expected but still. > > I'm flexible, if in the end this is what is required, that is fine. It > will need a comment explaining why it is needed, why the guidelines > are not being followed. > > Where i have real problems is with developers who don't respect what > the guidelines say, even when their hardware could do what is > asked. They just do the minimum to make it work, and call it done. > > The comment is then important, because i don't want developers using > this as an excuse not to do the correct thing. Sure, no problem. I'll add a comment in DT when I'll submit it, explaining what we have found regarding the PHY strapping and effects. > > Andrew -- Jerome