From mboxrd@z Thu Jan 1 00:00:00 1970 From: "David S. Miller" Subject: Re: [PATCH]snmp6 64-bit counter support in proc.c Date: Thu, 22 Jan 2004 16:35:04 -0800 (PST) Sender: netdev-bounce@oss.sgi.com Message-ID: <20040122.163504.74739809.davem@redhat.com> References: Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Cc: kuznet@ms2.inr.ac.ru, mashirle@us.ibm.com, netdev@oss.sgi.com, xma@us.ibm.com Return-path: To: kumarkr@us.ibm.com In-Reply-To: Errors-to: netdev-bounce@oss.sgi.com List-Id: netdev.vger.kernel.org From: Krishna Kumar Date: Thu, 22 Jan 2004 14:50:15 -0800 Isn't memory barrier used to stop re-ordering of instructions and needs to be present in both reader as well as writer to have synchronization since mb is for the CPU on which it is executing ? You are correct. Good thing I delayed this for a release, now we can work on making sure we get this right. :-)