From: Greg Banks <gnb@sgi.com>
To: Michael Chan <mchan@broadcom.com>
Cc: "David S. Miller" <davem@redhat.com>, netdev@oss.sgi.com
Subject: Re: [PATCH] fix BUG in tg3_tx
Date: Thu, 27 May 2004 02:04:43 +1000 [thread overview]
Message-ID: <20040526160443.GD4557@sgi.com> (raw)
In-Reply-To: <B1508D50A0692F42B217C22C02D849727FEDB8@NT-IRVA-0741.brcm.ad.broadcom.com>
On Tue, May 25, 2004 at 01:04:24PM -0700, Michael Chan wrote:
> [...] A few years ago we saw cases where there were tx completions
> on BDs that had not been sent. It turned out that on that machine, the
> chipset was re-ordering the posted mmio writes to the send mailbox
> register from 2 CPUs.[...]
On a related note, is there a good reason why the tg3 driver uses
the on-chip SRAM send ring by default instead of the host send ring?
This seems like it would dramatically increase the PIO load on the
chipset for some of the workloads I'm interested in.
Greg.
--
Greg Banks, R&D Software Engineer, SGI Australian Software Group.
I don't speak for SGI.
next prev parent reply other threads:[~2004-05-26 16:04 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-05-25 20:04 [PATCH] fix BUG in tg3_tx Michael Chan
2004-05-26 0:54 ` Greg Banks
2004-05-26 16:04 ` Greg Banks [this message]
2004-05-26 18:01 ` David S. Miller
2004-05-26 23:47 ` Greg Banks
2004-05-26 23:52 ` David S. Miller
2004-05-27 0:12 ` Greg Banks
-- strict thread matches above, loose matches on Subject: below --
2004-05-26 17:43 Michael Chan
2004-05-26 18:47 ` David S. Miller
2004-05-26 23:52 ` Greg Banks
2004-05-26 23:50 ` Greg Banks
2004-05-26 1:22 Michael Chan
2004-05-24 17:33 Michael Chan
2004-05-24 17:26 Michael Chan
2004-05-24 7:26 Greg Banks
2004-05-24 7:40 ` David S. Miller
2004-05-24 8:04 ` Greg Banks
2004-05-24 17:06 ` David S. Miller
2004-05-25 1:04 ` Greg Banks
2004-05-25 17:51 ` David S. Miller
2004-05-26 0:12 ` Greg Banks
2004-05-25 17:52 ` David S. Miller
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