[0/9][2.6] via-rhine patches

[0/9][2.6] via-rhine patches

[Roger Luethi]

More changes for via-rhine, part of my clean-up effort to make via-rhine
easier to maintain.

After this batch, I have a few clean-up patches that are a tad more
intrusive, plus fixes for broken functionality and new features.

Big thanks to A.J. from VIA Networking Technologies, Inc. who has
provided detailed information on Rhine chip behavior. Without him,
many of the via-rhine patches to come would not have happened.

Roger

[1/9][PATCH 2.6] Nuke HAS_IP_COPYSUM

[Roger Luethi]

HAS_IP_COPYSUM has been utterly meaningless for a long time.

Signed-off-by: Roger Luethi <rl@hellgate.ch>

--- orig/drivers/net/via-rhine.c
+++ mod/drivers/net/via-rhine.c
@@ -1563,15 +1563,10 @@
 				   eth_copy_and_sum is memcpy for all archs so
 				   this is kind of pointless right now
 				   ... or? */
-#if HAS_IP_COPYSUM		/* Call copy + cksum if available. */
 				eth_copy_and_sum(skb,
 						 rp->rx_skbuff[entry]->tail,
 						 pkt_len, 0);
 				skb_put(skb, pkt_len);
-#else
-				memcpy(skb_put(skb, pkt_len),
-				       rp->rx_skbuff[entry]->tail, pkt_len);
-#endif
 				pci_dma_sync_single_for_device(rp->pdev,
 							       rp->rx_skbuff_dma[entry],
 							       rp->rx_buf_sz,

[2/9][PATCH 2.6] Nuke CanHaveMII and related code

[Roger Luethi]

All Rhines can have a MII.

Signed-off-by: Roger Luethi <rl@hellgate.ch>

--- orig/drivers/net/via-rhine.c
+++ mod/drivers/net/via-rhine.c
@@ -375,7 +375,7 @@
 
 
 enum chip_capability_flags {
-	CanHaveMII=1, HasESIPhy=2, HasDavicomPhy=4,
+	HasESIPhy=2, HasDavicomPhy=4,
 	ReqTxAlign=0x10, HasWOL=0x20,
 };
 
@@ -391,13 +391,13 @@
 static struct rhine_chip_info rhine_chip_info[] __devinitdata =
 {
 	{ "VIA VT86C100A Rhine", RHINE_IOTYPE, 128,
-	  CanHaveMII | ReqTxAlign | HasDavicomPhy },
+	  ReqTxAlign | HasDavicomPhy },
 	{ "VIA VT6102 Rhine-II", RHINE_IOTYPE, 256,
-	  CanHaveMII | HasWOL },
+	  HasWOL },
 	{ "VIA VT6105 Rhine-III", RHINE_IOTYPE, 256,
-	  CanHaveMII | HasWOL },
+	  HasWOL },
 	{ "VIA VT6105M Rhine-III", RHINE_IOTYPE, 256,
-	  CanHaveMII | HasWOL },
+	  HasWOL },
 };
 
 static struct pci_device_id rhine_pci_tbl[] =
@@ -635,6 +635,7 @@
 	long memaddr;
 	int io_size;
 	int pci_flags;
+	int phy, phy_idx = 0;
 #ifdef USE_MMIO
 	long ioaddr0;
 #endif
@@ -830,32 +831,29 @@
 
 	pci_set_drvdata(pdev, dev);
 
-	if (rp->drv_flags & CanHaveMII) {
-		int phy, phy_idx = 0;
-		rp->phys[0] = 1;		/* Standard for this chip. */
-		for (phy = 1; phy < 32 && phy_idx < MAX_MII_CNT; phy++) {
-			int mii_status = mdio_read(dev, phy, 1);
-			if (mii_status != 0xffff && mii_status != 0x0000) {
-				rp->phys[phy_idx++] = phy;
-				rp->mii_if.advertising = mdio_read(dev, phy, 4);
-				printk(KERN_INFO "%s: MII PHY found at address "
-				       "%d, status 0x%4.4x advertising %4.4x "
-				       "Link %4.4x.\n", dev->name, phy,
-				       mii_status, rp->mii_if.advertising,
-				       mdio_read(dev, phy, 5));
-
-				/* set IFF_RUNNING */
-				if (mii_status & BMSR_LSTATUS)
-					netif_carrier_on(dev);
-				else
-					netif_carrier_off(dev);
+	rp->phys[0] = 1;		/* Standard for this chip. */
+	for (phy = 1; phy < 32 && phy_idx < MAX_MII_CNT; phy++) {
+		int mii_status = mdio_read(dev, phy, 1);
+		if (mii_status != 0xffff && mii_status != 0x0000) {
+			rp->phys[phy_idx++] = phy;
+			rp->mii_if.advertising = mdio_read(dev, phy, 4);
+			printk(KERN_INFO "%s: MII PHY found at address "
+			       "%d, status 0x%4.4x advertising %4.4x "
+			       "Link %4.4x.\n", dev->name, phy,
+			       mii_status, rp->mii_if.advertising,
+			       mdio_read(dev, phy, 5));
+
+			/* set IFF_RUNNING */
+			if (mii_status & BMSR_LSTATUS)
+				netif_carrier_on(dev);
+			else
+				netif_carrier_off(dev);
 
-				break;
-			}
+			break;
 		}
-		rp->mii_cnt = phy_idx;
-		rp->mii_if.phy_id = rp->phys[0];
 	}
+	rp->mii_cnt = phy_idx;
+	rp->mii_if.phy_id = rp->phys[0];
 
 	/* Allow forcing the media type. */
 	if (option > 0) {
@@ -1800,9 +1798,6 @@
 	struct rhine_private *rp = netdev_priv(dev);
 	int rc;
 
-	if (!(rp->drv_flags & CanHaveMII))
-		return -EINVAL;
-
 	spin_lock_irq(&rp->lock);
 	rc = mii_ethtool_gset(&rp->mii_if, cmd);
 	spin_unlock_irq(&rp->lock);
@@ -1815,9 +1810,6 @@
 	struct rhine_private *rp = netdev_priv(dev);
 	int rc;
 
-	if (!(rp->drv_flags & CanHaveMII))
-		return -EINVAL;
-
 	spin_lock_irq(&rp->lock);
 	rc = mii_ethtool_sset(&rp->mii_if, cmd);
 	spin_unlock_irq(&rp->lock);
@@ -1829,9 +1821,6 @@
 {
 	struct rhine_private *rp = netdev_priv(dev);
 
-	if (!(rp->drv_flags & CanHaveMII))
-		return -EINVAL;
-
 	return mii_nway_restart(&rp->mii_if);
 }
 
@@ -1839,9 +1828,6 @@
 {
 	struct rhine_private *rp = netdev_priv(dev);
 
-	if (!(rp->drv_flags & CanHaveMII))
-		return 0;	/* -EINVAL */
-
 	return mii_link_ok(&rp->mii_if);
 }
 

[3/9][PATCH 2.6] Nuke HasESIPhy and related code

[Roger Luethi]

This has been dead code forever.

Signed-off-by: Roger Luethi <rl@hellgate.ch>

--- orig/drivers/net/via-rhine.c
+++ mod/drivers/net/via-rhine.c
@@ -375,7 +375,7 @@
 
 
 enum chip_capability_flags {
-	HasESIPhy=2, HasDavicomPhy=4,
+	HasDavicomPhy=4,
 	ReqTxAlign=0x10, HasWOL=0x20,
 };
 
@@ -1085,9 +1085,8 @@
 
 	/* The LED outputs of various MII xcvrs should be configured. */
 	/* For NS or Mison phys, turn on bit 1 in register 0x17 */
-	/* For ESI phys, turn on bit 7 in register 0x17. */
 	mdio_write(dev, rp->phys[0], 0x17, mdio_read(dev, rp->phys[0], 0x17) |
-		   (rp->drv_flags & HasESIPhy) ? 0x0080 : 0x0001);
+		   0x0001);
 }
 
 /* Read and write over the MII Management Data I/O (MDIO) interface. */

[4/9][PATCH 2.6] Nuke default_port, references to if_port, medialock

[Roger Luethi]

As is, code doesn't do anything useful.

Signed-off-by: Roger Luethi <rl@hellgate.ch>

--- orig/drivers/net/via-rhine.c
+++ mod/drivers/net/via-rhine.c
@@ -522,7 +522,6 @@
 	u16 chip_cmd;			/* Current setting for ChipCmd */
 
 	/* These values are keep track of the transceiver/media in use. */
-	unsigned int default_port:4;	/* Last dev->if_port value. */
 	u8 tx_thresh, rx_thresh;
 
 	/* MII transceiver section. */
@@ -810,7 +809,6 @@
 	if (option > 0) {
 		if (option & 0x220)
 			rp->mii_if.full_duplex = 1;
-		rp->default_port = option & 15;
 	}
 	if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
 		rp->mii_if.full_duplex = 1;
@@ -859,10 +857,7 @@
 	if (option > 0) {
 		if (option & 0x220)
 			rp->mii_if.full_duplex = 1;
-		rp->default_port = option & 0x3ff;
 		if (option & 0x330) {
-			/* FIXME: shouldn't someone check this variable? */
-			/* rp->medialock = 1; */
 			printk(KERN_INFO " Forcing %dMbs %s-duplex "
 				"operation.\n",
 			       (option & 0x300 ? 100 : 10),
@@ -1061,9 +1056,6 @@
 	rp->rx_thresh = 0x60;		/* Written in rhine_set_rx_mod/drivers/nete(). */
 	rp->mii_if.full_duplex = 0;
 
-	if (dev->if_port == 0)
-		dev->if_port = rp->default_port;
-
 	writel(rp->rx_ring_dma, ioaddr + RxRingPtr);
 	writel(rp->tx_ring_dma, ioaddr + TxRingPtr);
 
@@ -1254,8 +1246,6 @@
 	       dev->name, readw(ioaddr + IntrStatus),
 	       mdio_read(dev, rp->phys[0], MII_BMSR));
 
-	dev->if_port = 0;
-
 	/* protect against concurrent rx interrupts */
 	disable_irq(rp->pdev->irq);
 

[5/9][PATCH 2.6] Nuke all pci_flags

[Roger Luethi]

All this code together can be replaced with a single #ifdef USE_MMIO.

Signed-off-by: Roger Luethi <rl@hellgate.ch>

--- orig/drivers/net/via-rhine.c
+++ mod/drivers/net/via-rhine.c
@@ -354,11 +354,6 @@
    second only the 1234 card.
 */
 
-enum pci_flags_bit {
-	PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
-	PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,
-};
-
 enum rhine_chips {
 	VT86C100A = 0,
 	VT6102,
@@ -368,7 +363,6 @@
 
 struct rhine_chip_info {
 	const char *name;
-	u16 pci_flags;
 	int io_size;
 	int drv_flags;
 };
@@ -379,24 +373,19 @@
 	ReqTxAlign=0x10, HasWOL=0x20,
 };
 
-#ifdef USE_MMIO
-#define RHINE_IOTYPE (PCI_USES_MEM | PCI_USES_MASTER | PCI_ADDR1)
-#else
-#define RHINE_IOTYPE (PCI_USES_IO  | PCI_USES_MASTER | PCI_ADDR0)
-#endif
 /* Beware of PCI posted writes */
 #define IOSYNC	do { readb(dev->base_addr + StationAddr); } while (0)
 
 /* directly indexed by enum rhine_chips, above */
 static struct rhine_chip_info rhine_chip_info[] __devinitdata =
 {
-	{ "VIA VT86C100A Rhine", RHINE_IOTYPE, 128,
+	{ "VIA VT86C100A Rhine", 128,
 	  ReqTxAlign | HasDavicomPhy },
-	{ "VIA VT6102 Rhine-II", RHINE_IOTYPE, 256,
+	{ "VIA VT6102 Rhine-II", 256,
 	  HasWOL },
-	{ "VIA VT6105 Rhine-III", RHINE_IOTYPE, 256,
+	{ "VIA VT6105 Rhine-III", 256,
 	  HasWOL },
-	{ "VIA VT6105M Rhine-III", RHINE_IOTYPE, 256,
+	{ "VIA VT6105M Rhine-III", 256,
 	  HasWOL },
 };
 
@@ -633,7 +622,6 @@
 	long ioaddr;
 	long memaddr;
 	int io_size;
-	int pci_flags;
 	int phy, phy_idx = 0;
 #ifdef USE_MMIO
 	long ioaddr0;
@@ -649,7 +637,6 @@
 	card_idx++;
 	option = card_idx < MAX_UNITS ? options[card_idx] : 0;
 	io_size = rhine_chip_info[chip_id].io_size;
-	pci_flags = rhine_chip_info[chip_id].pci_flags;
 
 	if (pci_enable_device(pdev))
 		goto err_out;
@@ -671,8 +658,7 @@
 	ioaddr = pci_resource_start(pdev, 0);
 	memaddr = pci_resource_start(pdev, 1);
 
-	if (pci_flags & PCI_USES_MASTER)
-		pci_set_master(pdev);
+	pci_set_master(pdev);
 
 	dev = alloc_etherdev(sizeof(*rp));
 	if (dev == NULL) {
@@ -821,7 +807,12 @@
 
 	printk(KERN_INFO "%s: %s at 0x%lx, ",
 	       dev->name, rhine_chip_info[chip_id].name,
-	       (pci_flags & PCI_USES_IO) ? ioaddr : memaddr);
+#ifdef USE_MMIO
+		memaddr
+#else
+		ioaddr
+#endif
+		 );
 
 	for (i = 0; i < 5; i++)
 		printk("%2.2x:", dev->dev_addr[i]);

[6/9][PATCH 2.6] Return codes for rhine_init_one

[Roger Luethi]

Use return codes in rhine_init_one instead of -ENODEV for all errors.

Signed-off-by: Roger Luethi <rl@hellgate.ch>

--- orig/drivers/net/via-rhine.c
+++ mod/drivers/net/via-rhine.c
@@ -616,7 +616,7 @@
 {
 	struct net_device *dev;
 	struct rhine_private *rp;
-	int i, option;
+	int i, option, rc;
 	int chip_id = (int) ent->driver_data;
 	static int card_idx = -1;
 	long ioaddr;
@@ -638,11 +638,13 @@
 	option = card_idx < MAX_UNITS ? options[card_idx] : 0;
 	io_size = rhine_chip_info[chip_id].io_size;
 
-	if (pci_enable_device(pdev))
+	rc = pci_enable_device(pdev);
+	if (rc)
 		goto err_out;
 
 	/* this should always be supported */
-	if (pci_set_dma_mask(pdev, 0xffffffff)) {
+	rc = pci_set_dma_mask(pdev, 0xffffffff);
+	if (rc) {
 		printk(KERN_ERR "32-bit PCI DMA addresses not supported by "
 		       "the card!?\n");
 		goto err_out;
@@ -651,6 +653,7 @@
 	/* sanity check */
 	if ((pci_resource_len(pdev, 0) < io_size) ||
 	    (pci_resource_len(pdev, 1) < io_size)) {
+		rc = -EIO;
 		printk(KERN_ERR "Insufficient PCI resources, aborting\n");
 		goto err_out;
 	}
@@ -662,6 +665,7 @@
 
 	dev = alloc_etherdev(sizeof(*rp));
 	if (dev == NULL) {
+		rc = -ENOMEM;
 		printk(KERN_ERR "init_ethernet failed for card #%d\n",
 		       card_idx);
 		goto err_out;
@@ -669,7 +673,8 @@
 	SET_MODULE_OWNER(dev);
 	SET_NETDEV_DEV(dev, &pdev->dev);
 
-	if (pci_request_regions(pdev, shortname))
+	rc = pci_request_regions(pdev, shortname);
+	if (rc)
 		goto err_out_free_netdev;
 
 #ifdef USE_MMIO
@@ -678,6 +683,7 @@
 
 	ioaddr = (long) ioremap(memaddr, io_size);
 	if (!ioaddr) {
+		rc = -EIO;
 		printk(KERN_ERR "ioremap failed for device %s, region 0x%X "
 		       "@ 0x%lX\n", pci_name(pdev), io_size, memaddr);
 		goto err_out_free_res;
@@ -690,6 +696,7 @@
 		unsigned char a = inb(ioaddr0+reg);
 		unsigned char b = readb(ioaddr+reg);
 		if (a != b) {
+			rc = -EIO;
 			printk(KERN_ERR "MMIO do not match PIO [%02x] "
 			       "(%02x != %02x)\n", reg, a, b);
 			goto err_out_unmap;
@@ -736,6 +743,7 @@
 		dev->dev_addr[i] = readb(ioaddr + StationAddr + i);
 
 	if (!is_valid_ether_addr(dev->dev_addr)) {
+		rc = -EIO;
 		printk(KERN_ERR "Invalid MAC address for card #%d\n", card_idx);
 		goto err_out_unmap;
 	}
@@ -787,8 +795,8 @@
 		dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
 
 	/* dev->name not defined before register_netdev()! */
-	i = register_netdev(dev);
-	if (i)
+	rc = register_netdev(dev);
+	if (rc)
 		goto err_out_unmap;
 
 	/* The lower four bits are the media type. */
@@ -871,7 +879,7 @@
 err_out_free_netdev:
 	free_netdev(dev);
 err_out:
-	return -ENODEV;
+	return rc;
 }
 
 static int alloc_ring(struct net_device* dev)

[7/9][PATCH 2.6] Rewrite special-casing

[Roger Luethi]

Use PCI revision to determine special cases. One bit field replaces a
bunch of data structures holding special case information.

Replace chip_id, drv_flags in rhine_private with quirks

Remove enum rhine_chips, struct rhine_chip_info (and array),
enum chip_capability_flags

Add enum rhine_revs, enum rhine_quirks (some values in preparation for
subsequent changes)

wait_for_reset() and enable_mmio() now use quirks instead of chip_id

Remove model names from ident strings for now.

Signed-off-by: Roger Luethi <rl@hellgate.ch>

--- orig/drivers/net/via-rhine.c
+++ mod/drivers/net/via-rhine.c
@@ -354,48 +354,46 @@
    second only the 1234 card.
 */
 
-enum rhine_chips {
-	VT86C100A = 0,
-	VT6102,
-	VT6105,
-	VT6105M
+enum rhine_revs {
+	VT86C100A	= 0x00,
+	VT6102		= 0x40,
+	VT8231		= 0x50,	/* Integrated MAC */
+	VT8233		= 0x60,	/* Integrated MAC */
+	VT8235		= 0x74,	/* Integrated MAC */
+	VT8237		= 0x78,	/* Integrated MAC */
+	VTunknown0	= 0x7C,
+	VT6105		= 0x80,
+	VT6105_B0	= 0x83,
+	VT6105L		= 0x8A,
+	VT6107		= 0x8C,
+	VTunknown1	= 0x8E,
+	VT6105M		= 0x90,
 };
 
-struct rhine_chip_info {
-	const char *name;
-	int io_size;
-	int drv_flags;
-};
-
-
-enum chip_capability_flags {
-	HasDavicomPhy=4,
-	ReqTxAlign=0x10, HasWOL=0x20,
+enum rhine_quirks {
+	rqWOL		= 0x0001,	/* Wake-On-LAN support */
+	rqForceReset	= 0x0002,
+	rqDavicomPhy	= 0x0020,
+	rq6patterns	= 0x0040,	/* 6 instead of 4 patterns for WOL */
+	rqStatusWBRace	= 0x0080,	/* Tx Status Writeback Error possible */
+	rqRhineI	= 0x0100,	/* See comment below */
 };
+/*
+ * rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable
+ * MMIO as well as for the collision counter and the Tx FIFO underflow
+ * indicator. In addition, Tx and Rx buffers need to 4 byte aligned.
+ */
 
 /* Beware of PCI posted writes */
 #define IOSYNC	do { readb(dev->base_addr + StationAddr); } while (0)
 
-/* directly indexed by enum rhine_chips, above */
-static struct rhine_chip_info rhine_chip_info[] __devinitdata =
-{
-	{ "VIA VT86C100A Rhine", 128,
-	  ReqTxAlign | HasDavicomPhy },
-	{ "VIA VT6102 Rhine-II", 256,
-	  HasWOL },
-	{ "VIA VT6105 Rhine-III", 256,
-	  HasWOL },
-	{ "VIA VT6105M Rhine-III", 256,
-	  HasWOL },
-};
-
 static struct pci_device_id rhine_pci_tbl[] =
 {
-	{0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VT86C100A},
-	{0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VT6102},
-	{0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VT6105}, /* 6105{,L,LOM} */
-	{0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VT6105M},
-	{0,}	/* terminate list */
+	{0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, /* VT86C100A */
+	{0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, /* VT6102 */
+	{0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, /* 6105{,L,LOM} */
+	{0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, /* VT6105M */
+	{ }	/* terminate list */
 };
 MODULE_DEVICE_TABLE(pci, rhine_pci_tbl);
 
@@ -503,7 +501,7 @@
 	spinlock_t lock;
 
 	/* Frequently used values: keep some adjacent for cache effect. */
-	int chip_id, drv_flags;
+	u32 quirks;
 	struct rx_desc *rx_head_desc;
 	unsigned int cur_rx, dirty_rx;	/* Producer/consumer ring indices */
 	unsigned int cur_tx, dirty_tx;
@@ -545,12 +543,12 @@
 
 	intr_status = readw(ioaddr + IntrStatus);
 	/* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
-	if (rp->chip_id == VT6102)
+	if (rp->quirks & rqStatusWBRace)
 		intr_status |= readb(ioaddr + IntrStatus2) << 16;
 	return intr_status;
 }
 
-static void wait_for_reset(struct net_device *dev, int chip_id, char *name)
+static void wait_for_reset(struct net_device *dev, u32 quirks, char *name)
 {
 	long ioaddr = dev->base_addr;
 	int boguscnt = 20;
@@ -562,7 +560,7 @@
 			"Trying harder.\n", name);
 
 		/* Rhine-II needs to be forced sometimes */
-		if (chip_id == VT6102)
+		if (quirks & rqForceReset)
 			writeb(0x40, ioaddr + MiscCmd);
 
 		/* VT86C100A may need long delay after reset (dlink) */
@@ -578,10 +576,10 @@
 }
 
 #ifdef USE_MMIO
-static void __devinit enable_mmio(long ioaddr, int chip_id)
+static void __devinit enable_mmio(long ioaddr, u32 quirks)
 {
 	int n;
-	if (chip_id == VT86C100A) {
+	if (quirks & rqRhineI) {
 		/* More recent docs say that this bit is reserved ... */
 		n = inb(ioaddr + ConfigA) | 0x20;
 		outb(n, ioaddr + ConfigA);
@@ -617,7 +615,8 @@
 	struct net_device *dev;
 	struct rhine_private *rp;
 	int i, option, rc;
-	int chip_id = (int) ent->driver_data;
+	u8 pci_rev;
+	u32 quirks;
 	static int card_idx = -1;
 	long ioaddr;
 	long memaddr;
@@ -626,6 +625,7 @@
 #ifdef USE_MMIO
 	long ioaddr0;
 #endif
+	const char *name;
 
 /* when built into the kernel, we only print version if device is found */
 #ifndef MODULE
@@ -636,7 +636,26 @@
 
 	card_idx++;
 	option = card_idx < MAX_UNITS ? options[card_idx] : 0;
-	io_size = rhine_chip_info[chip_id].io_size;
+	pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
+
+	io_size = 256;
+	if (pci_rev < VT6102) {
+		quirks = rqRhineI | rqDavicomPhy;
+		io_size = 128;
+		name = "VT86C100A Rhine";
+	}
+	else {
+		quirks = rqWOL | rqForceReset;
+		if (pci_rev < VT6105) {
+			name = "Rhine II";
+			quirks |= rqStatusWBRace;	/* Rhine-II exclusive */
+		}
+		else {
+			name = "Rhine III";
+			if (pci_rev >= VT6105_B0)
+				quirks |= rq6patterns;
+		}
+	}
 
 	rc = pci_enable_device(pdev);
 	if (rc)
@@ -679,7 +698,7 @@
 
 #ifdef USE_MMIO
 	ioaddr0 = ioaddr;
-	enable_mmio(ioaddr0, chip_id);
+	enable_mmio(ioaddr0, quirks);
 
 	ioaddr = (long) ioremap(memaddr, io_size);
 	if (!ioaddr) {
@@ -705,7 +724,7 @@
 #endif /* USE_MMIO */
 
 	/* D-Link provided reset code (with comment additions) */
-	if (rhine_chip_info[chip_id].drv_flags & HasWOL) {
+	if (quirks & rqWOL) {
 		unsigned char byOrgValue;
 
 		/* clear sticky bit before reset & read ethernet address */
@@ -726,7 +745,7 @@
 	writew(CmdReset, ioaddr + ChipCmd);
 
 	dev->base_addr = ioaddr;
-	wait_for_reset(dev, chip_id, shortname);
+	wait_for_reset(dev, quirks, shortname);
 
 	/* Reload the station address from the EEPROM. */
 #ifdef USE_MMIO
@@ -734,7 +753,7 @@
 	/* Reloading from eeprom overwrites cfgA-D, so we must re-enable MMIO.
 	   If reload_eeprom() was done first this could be avoided, but it is
 	   not known if that still works with the "win98-reboot" problem. */
-	enable_mmio(ioaddr0, chip_id);
+	enable_mmio(ioaddr0, quirks);
 #else
 	reload_eeprom(ioaddr);
 #endif
@@ -748,7 +767,7 @@
 		goto err_out_unmap;
 	}
 
-	if (chip_id == VT6102) {
+	if (quirks & rqWOL) {
 		/*
 		 * for 3065D, EEPROM reloaded will cause bit 0 in MAC_REG_CFGA
 		 * turned on. it makes MAC receive magic packet
@@ -766,9 +785,8 @@
 
 	rp = netdev_priv(dev);
 	spin_lock_init(&rp->lock);
-	rp->chip_id = chip_id;
-	rp->drv_flags = rhine_chip_info[chip_id].drv_flags;
 	rp->pdev = pdev;
+	rp->quirks = quirks;
 	rp->mii_if.dev = dev;
 	rp->mii_if.mdio_read = mdio_read;
 	rp->mii_if.mdio_write = mdio_write;
@@ -791,7 +809,7 @@
 #ifdef CONFIG_NET_POLL_CONTROLLER
 	dev->poll_controller = rhine_poll;
 #endif
-	if (rp->drv_flags & ReqTxAlign)
+	if (rp->quirks & rqRhineI)
 		dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
 
 	/* dev->name not defined before register_netdev()! */
@@ -813,8 +831,8 @@
 		rp->mii_if.force_media = 1;
 	}
 
-	printk(KERN_INFO "%s: %s at 0x%lx, ",
-	       dev->name, rhine_chip_info[chip_id].name,
+	printk(KERN_INFO "%s: VIA %s at 0x%lx, ",
+	       dev->name, name,
 #ifdef USE_MMIO
 		memaddr
 #else
@@ -896,7 +914,7 @@
 		printk(KERN_ERR "Could not allocate DMA memory.\n");
 		return -ENOMEM;
 	}
-	if (rp->drv_flags & ReqTxAlign) {
+	if (rp->quirks & rqRhineI) {
 		rp->tx_bufs = pci_alloc_consistent(rp->pdev,
 						   PKT_BUF_SZ * TX_RING_SIZE,
 						   &rp->tx_bufs_dma);
@@ -1154,7 +1172,7 @@
 		return i;
 	alloc_rbufs(dev);
 	alloc_tbufs(dev);
-	wait_for_reset(dev, rp->chip_id, dev->name);
+	wait_for_reset(dev, rp->quirks, dev->name);
 	init_registers(dev);
 	if (debug > 2)
 		printk(KERN_DEBUG "%s: Done rhine_open(), status %4.4x "
@@ -1260,7 +1278,7 @@
 	alloc_rbufs(dev);
 
 	/* Reinitialize the hardware. */
-	wait_for_reset(dev, rp->chip_id, dev->name);
+	wait_for_reset(dev, rp->quirks, dev->name);
 	init_registers(dev);
 
 	spin_unlock(&rp->lock);
@@ -1291,7 +1309,7 @@
 
 	rp->tx_skbuff[entry] = skb;
 
-	if ((rp->drv_flags & ReqTxAlign) &&
+	if ((rp->quirks & rqRhineI) &&
 	    (((long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_HW)) {
 		/* Must use alignment buffer. */
 		if (skb->len > PKT_BUF_SZ) {
@@ -1440,7 +1458,7 @@
 			if (txstatus & 0x0200) rp->stats.tx_window_errors++;
 			if (txstatus & 0x0100) rp->stats.tx_aborted_errors++;
 			if (txstatus & 0x0080) rp->stats.tx_heartbeat_errors++;
-			if (((rp->chip_id == VT86C100A) && txstatus & 0x0002) ||
+			if (((rp->quirks & rqRhineI) && txstatus & 0x0002) ||
 			    (txstatus & 0x0800) || (txstatus & 0x1000)) {
 				rp->stats.tx_fifo_errors++;
 				rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
@@ -1448,7 +1466,7 @@
 			}
 			/* Transmitter restarted in 'abnormal' handler. */
 		} else {
-			if (rp->chip_id == VT86C100A)
+			if (rp->quirks & rqRhineI)
 				rp->stats.collisions += (txstatus >> 3) & 0x0F;
 			else
 				rp->stats.collisions += txstatus & 0x0F;
@@ -1660,7 +1678,7 @@
 	if (intr_status & (IntrLinkChange)) {
 		if (readb(ioaddr + MIIStatus) & 0x02) {
 			/* Link failed, restart autonegotiation. */
-			if (rp->drv_flags & HasDavicomPhy)
+			if (rp->quirks & rqRhineI)
 				mdio_write(dev, rp->phys[0], MII_BMCR, 0x3300);
 		} else
 			rhine_check_duplex(dev);

[8/9][PATCH 2.6] Add rhine_power_init(): get power regs into sane state

[Roger Luethi]

Add rhine_power_init(): get power regs into sane state.
Move the respective code out of rhine_init_one. Add code for
two additional patterns (Rhine III).

Signed-off-by: Roger Luethi <rl@hellgate.ch>

--- orig/drivers/net/via-rhine.c
+++ mod/drivers/net/via-rhine.c
@@ -408,8 +408,10 @@
 	MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
 	ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
 	RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
-	StickyHW=0x83, IntrStatus2=0x84, WOLcrClr=0xA4, WOLcgClr=0xA7,
-	PwrcsrClr=0xAC,
+	StickyHW=0x83, IntrStatus2=0x84,
+	WOLcrSet=0xA0, WOLcrClr=0xA4, WOLcrClr1=0xA6,
+	WOLcgClr=0xA7,
+	PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD,
 };
 
 /* Bits in ConfigD */
@@ -548,6 +550,35 @@
 	return intr_status;
 }
 
+/*
+ * Get power related registers into sane state.
+ * Returns content of power-event (WOL) registers.
+ */
+static void rhine_power_init(struct net_device *dev)
+{
+	long ioaddr = dev->base_addr;
+	struct rhine_private *rp = netdev_priv(dev);
+
+	if (rp->quirks & rqWOL) {
+		/* Make sure chip is in power state D0 */
+		writeb(readb(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);
+
+		/* Disable "force PME-enable" */
+		writeb(0x80, ioaddr + WOLcgClr);
+
+		/* Clear power-event config bits (WOL) */
+		writeb(0xFF, ioaddr + WOLcrClr);
+		/* More recent cards can manage two additional patterns */
+		if (rp->quirks & rq6patterns)
+			writeb(0x03, ioaddr + WOLcrClr1);
+
+		/* Clear power-event status bits */
+		writeb(0xFF, ioaddr + PwrcsrClr);
+		if (rp->quirks & rq6patterns)
+			writeb(0x03, ioaddr + PwrcsrClr1);
+	}
+}
+
 static void wait_for_reset(struct net_device *dev, u32 quirks, char *name)
 {
 	long ioaddr = dev->base_addr;
@@ -722,29 +753,13 @@
 		}
 	}
 #endif /* USE_MMIO */
+	dev->base_addr = ioaddr;
 
-	/* D-Link provided reset code (with comment additions) */
-	if (quirks & rqWOL) {
-		unsigned char byOrgValue;
-
-		/* clear sticky bit before reset & read ethernet address */
-		byOrgValue = readb(ioaddr + StickyHW);
-		byOrgValue = byOrgValue & 0xFC;
-		writeb(byOrgValue, ioaddr + StickyHW);
-
-		/* (bits written are cleared?) */
-		/* disable force PME-enable */
-		writeb(0x80, ioaddr + WOLcgClr);
-		/* disable power-event config bit */
-		writeb(0xFF, ioaddr + WOLcrClr);
-		/* clear power status (undocumented in vt6102 docs?) */
-		writeb(0xFF, ioaddr + PwrcsrClr);
-	}
+	rhine_power_init(dev);
 
 	/* Reset the chip to erase previous misconfiguration. */
 	writew(CmdReset, ioaddr + ChipCmd);
 
-	dev->base_addr = ioaddr;
 	wait_for_reset(dev, quirks, shortname);
 
 	/* Reload the station address from the EEPROM. */

[9/9][PATCH 2.6] Restructure reset code

[Roger Luethi]

Restructure code to make it easier to maintain.

rhine_hw_init: resets chip, reloads eeprom
rhine_chip_reset: chip reset + what used to be wait_for_reset
rhine_reload_eeprom: reload eeprom, re-enable MMIO, disable EEPROM-controlled
	WOL

Note: Chip reset clears a bunch of registers that should be reloaded
from EEPROM (which turns off MMIO). Deal with that later.

Signed-off-by: Roger Luethi <rl@hellgate.ch>

--- orig/drivers/net/via-rhine.c
+++ mod/drivers/net/via-rhine.c
@@ -579,56 +579,76 @@
 	}
 }
 
-static void wait_for_reset(struct net_device *dev, u32 quirks, char *name)
+static void rhine_chip_reset(struct net_device *dev)
 {
 	long ioaddr = dev->base_addr;
+	struct rhine_private *rp = netdev_priv(dev);
 	int boguscnt = 20;
 
+	writew(CmdReset, ioaddr + ChipCmd);
 	IOSYNC;
 
 	if (readw(ioaddr + ChipCmd) & CmdReset) {
 		printk(KERN_INFO "%s: Reset not complete yet. "
-			"Trying harder.\n", name);
+			"Trying harder.\n", DRV_NAME);
 
-		/* Rhine-II needs to be forced sometimes */
-		if (quirks & rqForceReset)
+		/* Force reset */
+		if (rp->quirks & rqForceReset)
 			writeb(0x40, ioaddr + MiscCmd);
 
-		/* VT86C100A may need long delay after reset (dlink) */
-		/* Seen on Rhine-II as well (rl) */
+		/* Reset can take somewhat longer (rare) */
 		while ((readw(ioaddr + ChipCmd) & CmdReset) && --boguscnt)
 			udelay(5);
-
 	}
 
 	if (debug > 1)
-		printk(KERN_INFO "%s: Reset %s.\n", name,
+		printk(KERN_INFO "%s: Reset %s.\n", pci_name(rp->pdev),
 			boguscnt ? "succeeded" : "failed");
 }
 
 #ifdef USE_MMIO
-static void __devinit enable_mmio(long ioaddr, u32 quirks)
+static void __devinit enable_mmio(long pioaddr, u32 quirks)
 {
 	int n;
 	if (quirks & rqRhineI) {
 		/* More recent docs say that this bit is reserved ... */
-		n = inb(ioaddr + ConfigA) | 0x20;
-		outb(n, ioaddr + ConfigA);
+		n = inb(pioaddr + ConfigA) | 0x20;
+		outb(n, pioaddr + ConfigA);
 	} else {
-		n = inb(ioaddr + ConfigD) | 0x80;
-		outb(n, ioaddr + ConfigD);
+		n = inb(pioaddr + ConfigD) | 0x80;
+		outb(n, pioaddr + ConfigD);
 	}
 }
 #endif
 
-static void __devinit reload_eeprom(long ioaddr)
+/*
+ * Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM
+ */
+static void __devinit rhine_reload_eeprom(long pioaddr, struct net_device *dev)
 {
+	long ioaddr = dev->base_addr;
+	struct rhine_private *rp = netdev_priv(dev);
 	int i;
-	outb(0x20, ioaddr + MACRegEEcsr);
+
+	outb(0x20, pioaddr + MACRegEEcsr);
 	/* Typically 2 cycles to reload. */
 	for (i = 0; i < 150; i++)
-		if (! (inb(ioaddr + MACRegEEcsr) & 0x20))
+		if (! (inb(pioaddr + MACRegEEcsr) & 0x20))
 			break;
+
+#ifdef USE_MMIO
+	/*
+	 * Reloading from EEPROM overwrites ConfigA-D, so we must re-enable
+	 * MMIO. If reloading EEPROM was done first this could be avoided, but
+	 * it is not known if that still works with the "win98-reboot" problem.
+	 */
+	enable_mmio(pioaddr, rp->quirks);
+#endif
+
+	/* Turn off EEPROM-controlled wake-up (magic packet) */
+	if (rp->quirks & rqWOL)
+		writeb(readb(ioaddr + ConfigA) & 0xFE, ioaddr + ConfigA);
+
 }
 
 #ifdef CONFIG_NET_POLL_CONTROLLER
@@ -640,6 +660,15 @@
 }
 #endif
 
+static void rhine_hw_init(struct net_device *dev, long pioaddr)
+{
+	/* Reset the chip to erase previous misconfiguration. */
+	rhine_chip_reset(dev);
+
+	/* Reload EEPROM controlled bytes cleared by soft reset */
+	rhine_reload_eeprom(pioaddr, dev);
+}
+
 static int __devinit rhine_init_one(struct pci_dev *pdev,
 				    const struct pci_device_id *ent)
 {
@@ -649,13 +678,11 @@
 	u8 pci_rev;
 	u32 quirks;
 	static int card_idx = -1;
-	long ioaddr;
+	long pioaddr;
 	long memaddr;
+	long ioaddr;
 	int io_size;
 	int phy, phy_idx = 0;
-#ifdef USE_MMIO
-	long ioaddr0;
-#endif
 	const char *name;
 
 /* when built into the kernel, we only print version if device is found */
@@ -708,7 +735,7 @@
 		goto err_out;
 	}
 
-	ioaddr = pci_resource_start(pdev, 0);
+	pioaddr = pci_resource_start(pdev, 0);
 	memaddr = pci_resource_start(pdev, 1);
 
 	pci_set_master(pdev);
@@ -728,8 +755,7 @@
 		goto err_out_free_netdev;
 
 #ifdef USE_MMIO
-	ioaddr0 = ioaddr;
-	enable_mmio(ioaddr0, quirks);
+	enable_mmio(pioaddr, quirks);
 
 	ioaddr = (long) ioremap(memaddr, io_size);
 	if (!ioaddr) {
@@ -743,7 +769,7 @@
 	i = 0;
 	while (mmio_verify_registers[i]) {
 		int reg = mmio_verify_registers[i++];
-		unsigned char a = inb(ioaddr0+reg);
+		unsigned char a = inb(pioaddr+reg);
 		unsigned char b = readb(ioaddr+reg);
 		if (a != b) {
 			rc = -EIO;
@@ -752,26 +778,18 @@
 			goto err_out_unmap;
 		}
 	}
+#else
+	ioaddr = pioaddr;
 #endif /* USE_MMIO */
+
 	dev->base_addr = ioaddr;
+	rp = netdev_priv(dev);
+	rp->quirks = quirks;
 
 	rhine_power_init(dev);
 
 	/* Reset the chip to erase previous misconfiguration. */
-	writew(CmdReset, ioaddr + ChipCmd);
-
-	wait_for_reset(dev, quirks, shortname);
-
-	/* Reload the station address from the EEPROM. */
-#ifdef USE_MMIO
-	reload_eeprom(ioaddr0);
-	/* Reloading from eeprom overwrites cfgA-D, so we must re-enable MMIO.
-	   If reload_eeprom() was done first this could be avoided, but it is
-	   not known if that still works with the "win98-reboot" problem. */
-	enable_mmio(ioaddr0, quirks);
-#else
-	reload_eeprom(ioaddr);
-#endif
+	rhine_hw_init(dev, pioaddr);
 
 	for (i = 0; i < 6; i++)
 		dev->dev_addr[i] = readb(ioaddr + StationAddr + i);
@@ -782,15 +800,6 @@
 		goto err_out_unmap;
 	}
 
-	if (quirks & rqWOL) {
-		/*
-		 * for 3065D, EEPROM reloaded will cause bit 0 in MAC_REG_CFGA
-		 * turned on. it makes MAC receive magic packet
-		 * automatically. So, we turn it off. (D-Link)
-		 */
-		writeb(readb(ioaddr + ConfigA) & 0xFE, ioaddr + ConfigA);
-	}
-
 	/* Select backoff algorithm */
 	if (backoff)
 		writeb(readb(ioaddr + ConfigD) & (0xF0 | backoff),
@@ -798,10 +807,8 @@
 
 	dev->irq = pdev->irq;
 
-	rp = netdev_priv(dev);
 	spin_lock_init(&rp->lock);
 	rp->pdev = pdev;
-	rp->quirks = quirks;
 	rp->mii_if.dev = dev;
 	rp->mii_if.mdio_read = mdio_read;
 	rp->mii_if.mdio_write = mdio_write;
@@ -1170,9 +1177,6 @@
 	long ioaddr = dev->base_addr;
 	int i;
 
-	/* Reset the chip. */
-	writew(CmdReset, ioaddr + ChipCmd);
-
 	i = request_irq(rp->pdev->irq, &rhine_interrupt, SA_SHIRQ, dev->name,
 			dev);
 	if (i)
@@ -1187,7 +1191,7 @@
 		return i;
 	alloc_rbufs(dev);
 	alloc_tbufs(dev);
-	wait_for_reset(dev, rp->quirks, dev->name);
+	rhine_chip_reset(dev);
 	init_registers(dev);
 	if (debug > 2)
 		printk(KERN_DEBUG "%s: Done rhine_open(), status %4.4x "
@@ -1283,9 +1287,6 @@
 
 	spin_lock(&rp->lock);
 
-	/* Reset the chip. */
-	writew(CmdReset, ioaddr + ChipCmd);
-
 	/* clear all descriptors */
 	free_tbufs(dev);
 	free_rbufs(dev);
@@ -1293,7 +1294,7 @@
 	alloc_rbufs(dev);
 
 	/* Reinitialize the hardware. */
-	wait_for_reset(dev, rp->quirks, dev->name);
+	rhine_chip_reset(dev);
 	init_registers(dev);
 
 	spin_unlock(&rp->lock);

Re: [9/9][PATCH 2.6] Restructure reset code

[Jeff Garzik]

applied patches 1 through 8, rejected 9 (for now)

Re: [0/9][2.6] via-rhine patches

[Roger Luethi]

On Wed, 02 Jun 2004 15:29:20 -0400, Jeff Garzik wrote:
> Question -- are any of these needed for the 2.6.7 Release Candidate?

No. Any significant change in driver behavior would be a bug. Patches
submitted so far are clean-up in preparation for functional changes
to come.

> I prefer to defer these to post-2.6.7 as cleanup patches, since they are 
> not bug fixes.

ACK. Please note, though, that I have another set of patches coming up
which will be quite a bit more intrusive and will need review and wider
testing. I plan to submit in time for 2.6.8-pre, even though some of
it may not make it into 2.6.8.

Roger

Re: [9/9][PATCH 2.6] Restructure reset code

[Roger Luethi]

On Wed, 02 Jun 2004 15:43:28 -0400, Jeff Garzik wrote:
> Roger Luethi wrote:
> >Restructure code to make it easier to maintain.
> >
> >rhine_hw_init: resets chip, reloads eeprom
> >rhine_chip_reset: chip reset + what used to be wait_for_reset
> >rhine_reload_eeprom: reload eeprom, re-enable MMIO, disable 
> >EEPROM-controlled
> >	WOL
> >
> >Note: Chip reset clears a bunch of registers that should be reloaded
> >from EEPROM (which turns off MMIO). Deal with that later.
> 
> 
> Rejected, two reasons:
> 
> 1) dev->dev_addr[] should be loaded from eeprom only once, at probe 
> time, not once for each hw init.  [this value should be written to the 
> chip's MAC address registers upon each dev->open() call]

We are in violent agreement, you are describing what the driver
does with and without patch 9 (unless I seriously botched the
splitting). Incidentally, rhine_hw_init gets called only once, at probe
time (further calls are to rhine_chip_reset).

The remaining problem with the reset stuff is this: Years ago, soft
resets were added to via-rhine in the vain hope it would fix something,
but soft resets overwrite some registers that need to be reloaded
from somewhere (it's more than just the MAC address). The proper fix
for this is to remove unnecessary soft resets (i.e. all but the one at
probe time) and/or restore the registers affected by a soft reset. But
that would go beyond a simple clean-up patch.

> 2) Your "Note:" worries me...  why not deal with this now?  :)

Mainly because I don't have all the information needed to positively
determine the proper solution -- not yet. "Dealing with it" will likely
mean removing two soft reset calls and documenting registers that are
clobbered by soft reset (just in case), but that doesn't fit into a
clean-up patch anyway.

In summary, patch 9 is simply what all conceivable solutions have in
common -- code clean-up.

Thanks for the review.

Roger

Re: [9/9][PATCH 2.6] Restructure reset code

[Roger Luethi]

On Wed, 02 Jun 2004 15:43:28 -0400, Jeff Garzik wrote:
> Roger Luethi wrote:
> >Restructure code to make it easier to maintain.
[...]
> Rejected, two reasons:
> 
> 1) dev->dev_addr[] should be loaded from eeprom only once, at probe 
> time, not once for each hw init.  [this value should be written to the 
> chip's MAC address registers upon each dev->open() call]
> 
> 2) Your "Note:" worries me...  why not deal with this now?  :)

I addressed your concerns in my June 2 reply, but the patch didn't
get merged. Meanwhile, I am maintaining a growing queue of via-rhine
patches that need review and wider testing -- what is missing to move
forward in -mm?

Roger

Re: [9/9][PATCH 2.6] Restructure reset code

[Andrew Morton]

Roger Luethi <rl@hellgate.ch> wrote:
>
> what is missing to move forward in -mm?

Sending the patches would be a good start ;)

Re: [9/9][PATCH 2.6] Restructure reset code

[Roger Luethi]

On Mon, 14 Jun 2004 03:40:27 -0700, Andrew Morton wrote:
> Roger Luethi <rl@hellgate.ch> wrote:
> >
> > what is missing to move forward in -mm?
> 
> Sending the patches would be a good start ;)

I would have to rediff and fix them all against a driver without patch
[9/9] from the previous series. ATM I can't see a good reason for doing
that since for everything I know, that patch was perfectly fine.

Roger