recommendations for NIC HW(/SW) design?

recommendations for NIC HW(/SW) design?

[Lennert Buytenhek]

Hi,

I'm working on a NIC driver for the Intel IXP network processor (I've
got an almost releasable version at this point), but now I'm wondering
about the following.  Because the chip is programmable and I'm writing
the firmware myself, I am more-or-less free to determine which features
the hardware will implement, and more-or-less free to define the
hardware-software interface.

Does any of you have any general recommendations for this?  Is there
anything I should certainly implement, or any design mistakes that I
should certainly avoid?

(Since the Intel IXP processor is just an ARM processor with a network
interface grafted onto the chip, a bunch of things that apply to PCI
NIC design might not apply here.)


thanks,
Lennert

Re: recommendations for NIC HW(/SW) design?

[David S. Miller]

On Sun, 26 Sep 2004 17:29:55 +0200
Lennert Buytenhek <buytenh@wantstofly.org> wrote:

> Does any of you have any general recommendations for this?  Is there
> anything I should certainly implement, or any design mistakes that I
> should certainly avoid?

The best thing I think the tg3 does is that it uses 3
rings for packet management.

There is one transmit ring, one receive ring, and "response"
ring.

The cpu only writes to the first two rings, and the chip
only writes to the third ring.  And this is great for cache
behavior on the bus.

Re: recommendations for NIC HW(/SW) design?

[Harald Welte]

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On Sun, Sep 26, 2004 at 05:29:55PM +0200, Lennert Buytenhek wrote:

> (Since the Intel IXP processor is just an ARM processor with a network
> interface grafted onto the chip, a bunch of things that apply to PCI
> NIC design might not apply here.)

I think this IXP is only a UP architecture, is it?  For SMP scalability
it would be nice to specify the Tx Interrupt in every descriptor, so you
can cause Tx interrupts go to the cpu that actually sent the packet
(cache locality).

> thanks,
> Lennert

-- 
- Harald Welte <laforge@gnumonks.org>               http://www.gnumonks.org/
============================================================================
Programming is like sex: One mistake and you have to support it your lifetime

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Re: recommendations for NIC HW(/SW) design?

[Lennert Buytenhek]

On Mon, Sep 27, 2004 at 05:51:44PM +0200, Harald Welte wrote:

> > (Since the Intel IXP processor is just an ARM processor with a network
> > interface grafted onto the chip, a bunch of things that apply to PCI
> > NIC design might not apply here.)
> 
> I think this IXP is only a UP architecture, is it?

Yeah, it's a single-core ARM with a big fat pipe (either 4 or 10 Gb/s
depending on model) grafted onto the CPU.


--L