From: "David S. Miller" <davem@davemloft.net>
To: Jesse Barnes <jbarnes@engr.sgi.com>
Cc: akpm@osdl.org, linux-kernel@vger.kernel.org, netdev@oss.sgi.com,
jgarzik@pobox.com, gnb@sgi.com, akepner@sgi.com
Subject: Re: [PATCH] use mmiowb in tg3.c
Date: Thu, 21 Oct 2004 16:40:07 -0700 [thread overview]
Message-ID: <20041021164007.4933b10b.davem@davemloft.net> (raw)
In-Reply-To: <200410211628.06906.jbarnes@engr.sgi.com>
On Thu, 21 Oct 2004 16:28:06 -0700
Jesse Barnes <jbarnes@engr.sgi.com> wrote:
> This patch originally from Greg Banks. Some parts of the tg3 driver depend on
> PIO writes arriving in order. This patch ensures that in two key places
> using the new mmiowb macro. This not only prevents bugs (the queues can be
> corrupted), but is much faster than ensuring ordering using PIO reads (which
> involve a few round trips to the target bus on some platforms).
Do other PCI systems which post PIO writes also potentially reorder
them just like this SGI system does? Just trying to get this situation
straight in my head.
next prev parent reply other threads:[~2004-10-21 23:40 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <200410211613.19601.jbarnes@engr.sgi.com>
2004-10-21 23:28 ` [PATCH] use mmiowb in tg3.c Jesse Barnes
2004-10-21 23:40 ` David S. Miller [this message]
2004-10-22 1:16 ` Benjamin Herrenschmidt
2004-10-22 1:33 ` akepner
2004-10-22 2:07 ` Benjamin Herrenschmidt
2004-10-22 3:01 ` Jesse Barnes
2004-10-22 4:00 ` Paul Mackerras
2004-10-22 20:51 ` [PATCH] use mmiowb in tg3_poll akepner
2005-05-28 23:12 ` Lennert Buytenhek
2005-05-30 16:30 ` Arthur Kepner
2005-05-31 12:53 ` jamal
2005-05-31 16:45 ` Jesse Barnes
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