From: "David S. Miller" <davem@davemloft.net>
To: "Michael Chan" <mchan@broadcom.com>
Cc: netdev@oss.sgi.com
Subject: Re: [PATCH 2.6.11 2/8] tg3: flush status block in tg3_interrupt
Date: Wed, 23 Mar 2005 11:07:00 -0800 [thread overview]
Message-ID: <20050323110700.0f071073.davem@davemloft.net> (raw)
In-Reply-To: <B1508D50A0692F42B217C22C02D84972020F3E22@NT-IRVA-0741.brcm.ad.broadcom.com>
On Sun, 20 Mar 2005 23:26:26 -0800
"Michael Chan" <mchan@broadcom.com> wrote:
> Add register read of PCI state register in tg3_interrupt() if status block's
> updated bit is not set. This will flush the status block and confirm whether
> the interrupt is ours or not. PCI ordering rules allow the interrupt to
> arrive at the CPU ahead of the status block that may be posted at the
> chipset.
>
> Signed-off-by: Michael Chan <mchan@broadcom.com>
Applied, thanks Michael.
prev parent reply other threads:[~2005-03-23 19:07 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-03-21 7:26 [PATCH 2.6.11 2/8] tg3: flush status block in tg3_interrupt Michael Chan
2005-03-22 20:53 ` Jeff Garzik
2005-03-23 19:07 ` David S. Miller [this message]
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