Re: tg3 support broken on PPC, a workaround

[Grant Grundler <iod00d@hp.com>]

On Tue, May 10, 2005 at 03:13:25PM -0700, Rick Jones wrote:
> David S. Miller wrote:
> >We really should be disconnecting at single cacheline boundaries
> >on RISC systems.  The PCI controllers on RISC machines are
> >going to disconnect the tg3 when it crosses a cache line
> >boundary, so all these setting do is waste PCI bandwidth.
> 
> It is my understanding that PA-RISC and IA64 controllers behave 
> differently. For confirmation one way or the other, I've cc'd someone who 
> could talk about it much more cogently than I.

Yup, thanks rick.

Dave,
HP PCI bus controllers don't disconnect after a cacheline.
The latest "LBA" (aka Mercury) will disconnect on 4k page
boundaries. Alex Williamson confirmed.

Has anyone confirmed PPC, PPC64 and Alpha PCI/PCI-X bus
controllers do the same?

ISTR MMRBC (PCI-X only) allows one to specify
shorter blocks. I'd have to look that up again.

thanks,
grant