From: "David S. Miller" <davem@davemloft.net>
To: mchan@broadcom.com
Cc: netdev@oss.sgi.com
Subject: Re: Locking model for NAPI drivers
Date: Wed, 01 Jun 2005 15:21:34 -0700 (PDT) [thread overview]
Message-ID: <20050601.152134.120445266.davem@davemloft.net> (raw)
In-Reply-To: <1117658019.4310.58.camel@rh4>
From: "Michael Chan" <mchan@broadcom.com>
Date: Wed, 01 Jun 2005 13:33:39 -0700
> I suppose we can enable interrupts in tg3_irq_quiesce() after setting
> the SYNC bit.
Since the caller shuts down NAPI ->poll(), after setting the SYNC bit
we can just check the MAILBOX register, and if a '1' is there just
return. Does one need to mask out the upper bits of the regiser in
order to avoid seeing the IRQ tag in such a comparison?
Another potential problem is if the chip is hung for some reason,
and even though an interrupt is asserted it does not send the
interrupt. We'd hang in this case as well. Therefore it may be
wise to add a timeout to the COMPLETE bit polling loop in order
to handle such cases properly.
next prev parent reply other threads:[~2005-06-01 22:21 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-05-31 22:48 Locking model for NAPI drivers David S. Miller
2005-06-01 6:28 ` Andi Kleen
2005-06-01 8:42 ` Herbert Xu
2005-06-01 8:16 ` Greg Banks
2005-06-01 20:33 ` Michael Chan
2005-06-01 22:21 ` David S. Miller [this message]
2005-06-01 21:34 ` Michael Chan
2005-06-02 19:56 ` Michael Chan
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