From mboxrd@z Thu Jan  1 00:00:00 1970
From: Andi Kleen <ak@suse.de>
Subject: Re: Timeline of IPoIB performance
Date: Tue, 11 Oct 2005 02:51:22 +0200
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To: Grant Grundler <iod00d@hp.com>
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On Tuesday 11 October 2005 01:30, Grant Grundler wrote:
> On Mon, Oct 10, 2005 at 02:26:52PM -0700, Grant Grundler wrote:
> ...
>
> > If it's interleaving, every other cacheline will be "local".
>
> ISTR AMD64 was page-interleaved but then got confused by documents
> describing "128-bit" 2-way interleave. I now realize the 128bit
> is refering to interleave between two "banks" of memory behind
> each memory controller. ie 2 * 128-bit provides in the 32-byte
> cacheline size that most x86 programs expect.

The cache line size on K7 and K8 is 64 bytes.

> Anyway, I'm hoping that we'll see a consistent result if node interleave
> is turned off.

Yes usually a good idea.


-Andi