From mboxrd@z Thu Jan  1 00:00:00 1970
From: "David S. Miller" <davem@davemloft.net>
Subject: Re: [PATCH] forcedeth: TSO fix for large buffers
Date: Sun, 25 Dec 2005 12:57:42 -0800 (PST)
Message-ID: <20051225.125742.65007619.davem@davemloft.net>
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Cc: jgarzik@pobox.com, aabdulla@nvidia.com, afu@fugmann.net,
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From: Manfred Spraul <manfred@dbl.q-ag.de>
Date: Sun, 25 Dec 2005 15:51:42 +0100

> This patch contains a bug fix for large buffers. Originally, if a tx 
> buffer to be sent was larger then the maximum size of the tx descriptor,
> 
> it would overwrite other control bits. In this patch, the buffer is 
> split over multiple descriptors. Also, the fragments are now setup in 
> forward order.
> 
> Signed-off-by: Ayaz Abdulla <aabdulla@nvidia.com>
> 
> Rediffed against forcedeth 0.48
> Signed-Off-By: Manfred Spraul <manfred@colorfullife.com>

Are you sure it's ok to setup the tx descriptors in that order?

Usually, you need to set them up last to first so that the chip
doesn't see a half-filled-in set of TX descriptors.  Ie. the
core question is if the chip can scan the TX descriptors looking
for valid ones all on it's own after processing existing TX
descriptors, or do you have to explicitly allow the chip look
at the newly added TX descriptor with a register write or similar?