From: linas@austin.ibm.com (Linas Vepstas)
To: "Brandeburg, Jesse" <jesse.brandeburg@intel.com>
Cc: "Ronciak, John" <john.ronciak@intel.com>,
cramerj <cramerj@intel.com>,
"Kirsher, Jeffrey T" <jeffrey.t.kirsher@intel.com>,
"Kok, Auke-jan H" <auke-jan.h.kok@intel.com>,
"Veeraiyan, Ayyappan" <ayyappan.veeraiyan@intel.com>,
netdev@vger.kernel.org
Subject: Re: ixgb EEH/PCI errors on reset
Date: Fri, 23 Jun 2006 16:33:39 -0500 [thread overview]
Message-ID: <20060623213339.GR8866@austin.ibm.com> (raw)
In-Reply-To: <Pine.WNT.4.63.0606231258110.3548@jbrandeb-desk.amr.corp.intel.com>
On Fri, Jun 23, 2006 at 01:15:53PM -0700, Brandeburg, Jesse wrote:
> > fails in an unexpected way. The last call invokes ixgb_mac_reset()
> > which writes a reset bit, delays a few millisecs, and reads the reset
> > bit. The problem I'm seeing is that the read
> >
> > ctrl_reg = IXGB_READ_REG(hw, CTRL0);
> >
> > triggers some PCI bus error that off-lines the device. Any hints
>
> try this patch? it is compile tested.
[...]
> IXGB_WRITE_REG(hw, EECD, *eecd_reg);
> + IXGB_WRITE_FLUSH(hw);
> udelay(50);
With such a response, I had high hopes that the patch would work.
Alas, it didn't help. I am in the process of rolling back to
the driver v 1.0.100, which doesn'thave the problem, to see
if I can isolate what changed.
--linas
prev parent reply other threads:[~2006-06-23 21:33 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-06-23 17:09 ixgb EEH/PCI errors on reset Linas Vepstas
2006-06-23 20:15 ` Brandeburg, Jesse
2006-06-23 21:33 ` Linas Vepstas [this message]
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