From mboxrd@z Thu Jan 1 00:00:00 1970 From: Valerie Henson Subject: [patch 04/10] [TULIP] Flush MMIO writes in reset sequence Date: Fri, 08 Sep 2006 11:15:37 -0700 Message-ID: <20060908182023.330738000@linux.intel.com> References: <20060908181533.771856000@linux.intel.com> Cc: Grant Grundler , Kyle McMartin , Valerie Henson , Jeff Garzik Return-path: To: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Content-Disposition: inline; filename=tulip-flush-mmio-writes-in-reset-sequence Sender: linux-kernel-owner@vger.kernel.org List-Id: netdev.vger.kernel.org From: Grant Grundler The obvious safe registers to read is one from PCI config space. Signed-off-by: Grant Grundler Signed-off-by: Kyle McMartin Signed-off-by: Valerie Henson Signed-off-by: Jeff Garzik --- drivers/net/tulip/tulip_core.c | 2 ++ 1 files changed, 2 insertions(+) --- linux-2.6.18-rc4-mm1.orig/drivers/net/tulip/tulip_core.c +++ linux-2.6.18-rc4-mm1/drivers/net/tulip/tulip_core.c @@ -295,12 +295,14 @@ static void tulip_up(struct net_device * /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */ iowrite32(0x00000001, ioaddr + CSR0); + pci_read_config_dword(tp->pdev, PCI_COMMAND, &i); /* flush write */ udelay(100); /* Deassert reset. Wait the specified 50 PCI cycles after a reset by initializing Tx and Rx queues and the address filter list. */ iowrite32(tp->csr0, ioaddr + CSR0); + pci_read_config_dword(tp->pdev, PCI_COMMAND, &i); /* flush write */ udelay(100); if (tulip_debug > 1) --