From: David Miller <davem@davemloft.net>
To: mchan@broadcom.com
Cc: linville@tuxdriver.com, netdev@vger.kernel.org
Subject: Re: [PATCH 6/9][TG3]: Add basic 5906 support.
Date: Wed, 27 Sep 2006 16:08:36 -0700 (PDT) [thread overview]
Message-ID: <20060927.160836.74560378.davem@davemloft.net> (raw)
In-Reply-To: <1159389299.3411.23.camel@rh4>
From: "Michael Chan" <mchan@broadcom.com>
Date: Wed, 27 Sep 2006 13:34:59 -0700
> [TG3]: Add basic 5906 support.
>
> Add support for the new 5709 device. This is a new 10/100 Mbps chip.
> The mailbox access and firmware interface are quite different from
> all other tg3 chips.
>
> Signed-off-by: Michael Chan <mchan@broadcom.com>
Looks fine, applied.
Quick question:
> @@ -491,6 +513,9 @@ static inline void tg3_cond_int(struct t
> if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
> (tp->hw_status->status & SD_STATUS_UPDATED))
> tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
> + else
> + tw32(HOSTCC_MODE, tp->coalesce_mode |
> + (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
> }
>
> static void tg3_enable_ints(struct tg3 *tp)
Why are we forcing a coalescing event here now? This seems
to apply in quite a large number of cases. It will trigger
if either:
1) using tagged status
2) SD_STATUS_UPDATED is not indicated in the status block
In particular, how is this a 5906 specific support change
when there are no 5906 or other chipset conditionals guarding
the logic here?
next prev parent reply other threads:[~2006-09-27 23:08 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-09-27 20:34 [PATCH 6/9][TG3]: Add basic 5906 support Michael Chan
2006-09-27 23:08 ` David Miller [this message]
2006-09-27 23:21 ` Michael Chan
2006-09-28 0:03 ` David Miller
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