Re: [PATCH]: Third (final?) release of Sun Neptune driver

Matheos Worku
2007-10-05T17:45:47Z

Ingo Oeser wrote:
> Hi David,
>
> some minor nits.
>
> Could this driver be split into more files. 8k lines per file
> is quite a lot. Although GCC might optimize it best this way :-)
>

Ingo,

Some r info on Neptune HW to explains some of the constants ...
Regards
Matheos

>> + ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
>> + ENET_SERDES_CTRL_SDET_1 |
>> + ENET_SERDES_CTRL_SDET_2 |
>> + ENET_SERDES_CTRL_SDET_3 |
>> + (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
>> + (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
>> + (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
>> + (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
>> + (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
>> + (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
>> + (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
>> + (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
>> + test_cfg_val = 0;
>> +
>> + if (lp->loopback_mode == LOOPBACK_PHY) {
>> + test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
>> + ENET_SERDES_TEST_MD_0_SHIFT) |
>> + (ENET_TEST_MD_PAD_LOOPBACK <<
>> + ENET_SERDES_TEST_MD_1_SHIFT) |
>> + (ENET_TEST_MD_PAD_LOOPBACK <<
>> + ENET_SERDES_TEST_MD_2_SHIFT) |
>> + (ENET_TEST_MD_PAD_LOOPBACK <<
>> + ENET_SERDES_TEST_MD_3_SHIFT));
>> + }
>> +
>> + nw64(ctrl_reg, ctrl_val);
>> + nw64(test_cfg_reg, test_cfg_val);
>> +
>> + for (i = 0; i < 4; i++) {
>>
>
> why 4? (magic number)
>
The MAC HW has 4 SERDES lanes. Need to configure each lane
>
>
>> +static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
>> +{
>> + int mtu = np->dev->mtu;
>> +
>> + rp->max_burst = mtu + 32;
>> + if (rp->max_burst > 4096)
>> + rp->max_burst = 4096;
>>
>
> Why 32 and 4096? (Magic values)
>
These values were recommended by the HW designers for fair utilization
of DRR feature among TX/RX rings.
>
>> +}
>> +
>>
>
> ... ok, I stop here, since this drivers is damn big :-)
>
> Best Regards
>
> Ingo Oeser
>