* [PATCH 01/26] atl1: relocate atl1 driver to /drivers/net/atlx
2008-01-01 2:22 [PATCH 00/26] atl1: divide and modernize Jay Cliburn
@ 2008-01-01 2:22 ` Jay Cliburn
2008-01-01 2:22 ` [PATCH 02/26] atl1: move common functions to atlx files Jay Cliburn
` (25 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Jay Cliburn @ 2008-01-01 2:22 UTC (permalink / raw)
To: netdev; +Cc: Jay Cliburn, Chris Snook
In preparation for a future Atheros L2 NIC driver (called atl2), relocate
the atl1 driver into a new /drivers/net/atlx directory that will ultimately
be shared with the future atl2 driver.
Signed-off-by: Chris Snook <csnook@redhat.com>
Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net>
---
drivers/net/Makefile | 2 +-
drivers/net/{atl1 => atlx}/Makefile | 0
drivers/net/{atl1 => atlx}/atl1.h | 0
drivers/net/{atl1 => atlx}/atl1_ethtool.c | 0
drivers/net/{atl1 => atlx}/atl1_hw.c | 0
drivers/net/{atl1 => atlx}/atl1_hw.h | 0
drivers/net/{atl1 => atlx}/atl1_main.c | 0
drivers/net/{atl1 => atlx}/atl1_param.c | 0
8 files changed, 1 insertions(+), 1 deletions(-)
rename drivers/net/{atl1 => atlx}/Makefile (100%)
rename drivers/net/{atl1 => atlx}/atl1.h (100%)
rename drivers/net/{atl1 => atlx}/atl1_ethtool.c (100%)
rename drivers/net/{atl1 => atlx}/atl1_hw.c (100%)
rename drivers/net/{atl1 => atlx}/atl1_hw.h (100%)
rename drivers/net/{atl1 => atlx}/atl1_main.c (100%)
rename drivers/net/{atl1 => atlx}/atl1_param.c (100%)
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 0e5fde4..14acf84 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -13,7 +13,7 @@ obj-$(CONFIG_CHELSIO_T1) += chelsio/
obj-$(CONFIG_CHELSIO_T3) += cxgb3/
obj-$(CONFIG_EHEA) += ehea/
obj-$(CONFIG_BONDING) += bonding/
-obj-$(CONFIG_ATL1) += atl1/
+obj-$(CONFIG_ATL1) += atlx/
obj-$(CONFIG_GIANFAR) += gianfar_driver.o
obj-$(CONFIG_TEHUTI) += tehuti.o
diff --git a/drivers/net/atl1/Makefile b/drivers/net/atlx/Makefile
similarity index 100%
rename from drivers/net/atl1/Makefile
rename to drivers/net/atlx/Makefile
diff --git a/drivers/net/atl1/atl1.h b/drivers/net/atlx/atl1.h
similarity index 100%
rename from drivers/net/atl1/atl1.h
rename to drivers/net/atlx/atl1.h
diff --git a/drivers/net/atl1/atl1_ethtool.c b/drivers/net/atlx/atl1_ethtool.c
similarity index 100%
rename from drivers/net/atl1/atl1_ethtool.c
rename to drivers/net/atlx/atl1_ethtool.c
diff --git a/drivers/net/atl1/atl1_hw.c b/drivers/net/atlx/atl1_hw.c
similarity index 100%
rename from drivers/net/atl1/atl1_hw.c
rename to drivers/net/atlx/atl1_hw.c
diff --git a/drivers/net/atl1/atl1_hw.h b/drivers/net/atlx/atl1_hw.h
similarity index 100%
rename from drivers/net/atl1/atl1_hw.h
rename to drivers/net/atlx/atl1_hw.h
diff --git a/drivers/net/atl1/atl1_main.c b/drivers/net/atlx/atl1_main.c
similarity index 100%
rename from drivers/net/atl1/atl1_main.c
rename to drivers/net/atlx/atl1_main.c
diff --git a/drivers/net/atl1/atl1_param.c b/drivers/net/atlx/atl1_param.c
similarity index 100%
rename from drivers/net/atl1/atl1_param.c
rename to drivers/net/atlx/atl1_param.c
--
1.5.3.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 02/26] atl1: move common functions to atlx files
2008-01-01 2:22 [PATCH 00/26] atl1: divide and modernize Jay Cliburn
2008-01-01 2:22 ` [PATCH 01/26] atl1: relocate atl1 driver to /drivers/net/atlx Jay Cliburn
@ 2008-01-01 2:22 ` Jay Cliburn
2008-01-01 2:22 ` [PATCH 03/26] atl1: fix broken TSO Jay Cliburn
` (24 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Jay Cliburn @ 2008-01-01 2:22 UTC (permalink / raw)
To: netdev; +Cc: Jay Cliburn, Chris Snook
The future atl2 driver and the existing atl1 driver can share certain
functions and definitions. Move these shareable functions and definitions
out of atl1-specific files and into atlx.c and atlx.h. Some transitory
hackery will be present until atl2 is merged.
Reduce the number of source files by moving ethtool, hw, and param
functions from separate files into atl1_main.c, then rename it to just
atl1.c.
Move all atl1-specific definitions from atl1_hw.h to atl1.h.
Finally, clean up to make checkpatch.pl happy.
Signed-off-by: Chris Snook <csnook@redhat.com>
Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net>
---
drivers/net/atlx/Makefile | 1 -
drivers/net/atlx/{atl1_main.c => atl1.c} | 1544 ++++++++++++++++++++++++------
drivers/net/atlx/atl1.h | 603 +++++++++++-
drivers/net/atlx/atl1_ethtool.c | 505 ----------
drivers/net/atlx/atl1_hw.c | 720 --------------
drivers/net/atlx/atl1_hw.h | 946 ------------------
drivers/net/atlx/atl1_param.c | 203 ----
drivers/net/atlx/atlx.c | 433 +++++++++
drivers/net/atlx/atlx.h | 506 ++++++++++
9 files changed, 2751 insertions(+), 2710 deletions(-)
rename drivers/net/atlx/{atl1_main.c => atl1.c} (65%)
delete mode 100644 drivers/net/atlx/atl1_ethtool.c
delete mode 100644 drivers/net/atlx/atl1_hw.c
delete mode 100644 drivers/net/atlx/atl1_hw.h
delete mode 100644 drivers/net/atlx/atl1_param.c
create mode 100644 drivers/net/atlx/atlx.c
create mode 100644 drivers/net/atlx/atlx.h
diff --git a/drivers/net/atlx/Makefile b/drivers/net/atlx/Makefile
index a6b707e..ca45553 100644
--- a/drivers/net/atlx/Makefile
+++ b/drivers/net/atlx/Makefile
@@ -1,2 +1 @@
obj-$(CONFIG_ATL1) += atl1.o
-atl1-y += atl1_main.o atl1_hw.o atl1_ethtool.o atl1_param.o
diff --git a/drivers/net/atlx/atl1_main.c b/drivers/net/atlx/atl1.c
similarity index 65%
rename from drivers/net/atlx/atl1_main.c
rename to drivers/net/atlx/atl1.c
index 35b0a7d..0df3f32 100644
--- a/drivers/net/atlx/atl1_main.c
+++ b/drivers/net/atlx/atl1.c
@@ -1,6 +1,6 @@
/*
* Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
- * Copyright(c) 2006 Chris Snook <csnook@redhat.com>
+ * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
* Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
*
* Derived from Intel e1000 driver
@@ -50,51 +50,46 @@
* SMP torture testing
*/
-#include <linux/types.h>
-#include <linux/netdevice.h>
-#include <linux/pci.h>
-#include <linux/spinlock.h>
-#include <linux/slab.h>
-#include <linux/string.h>
-#include <linux/skbuff.h>
+#include <asm/atomic.h>
+#include <asm/byteorder.h>
+
+#include <linux/compiler.h>
+#include <linux/crc32.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
#include <linux/etherdevice.h>
-#include <linux/if_vlan.h>
-#include <linux/if_ether.h>
-#include <linux/irqreturn.h>
-#include <linux/workqueue.h>
-#include <linux/timer.h>
-#include <linux/jiffies.h>
#include <linux/hardirq.h>
+#include <linux/if_ether.h>
+#include <linux/if_vlan.h>
+#include <linux/in.h>
#include <linux/interrupt.h>
+#include <linux/ip.h>
#include <linux/irqflags.h>
-#include <linux/dma-mapping.h>
+#include <linux/irqreturn.h>
+#include <linux/jiffies.h>
+#include <linux/mii.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
#include <linux/net.h>
+#include <linux/netdevice.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
#include <linux/pm.h>
-#include <linux/in.h>
-#include <linux/ip.h>
+#include <linux/skbuff.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/string.h>
#include <linux/tcp.h>
-#include <linux/compiler.h>
-#include <linux/delay.h>
-#include <linux/mii.h>
-#include <net/checksum.h>
+#include <linux/timer.h>
+#include <linux/types.h>
+#include <linux/workqueue.h>
-#include <asm/atomic.h>
-#include <asm/byteorder.h>
+#include <net/checksum.h>
#include "atl1.h"
-#define DRIVER_VERSION "2.0.7"
-
-char atl1_driver_name[] = "atl1";
-static const char atl1_driver_string[] = "Attansic L1 Ethernet Network Driver";
-static const char atl1_copyright[] = "Copyright(c) 2005-2006 Attansic Corporation.";
-char atl1_driver_version[] = DRIVER_VERSION;
-
-MODULE_AUTHOR
- ("Attansic Corporation <xiong_huang@attansic.com>, Chris Snook <csnook@redhat.com>, Jay Cliburn <jcliburn@gmail.com>");
-MODULE_DESCRIPTION("Attansic 1000M Ethernet Network Driver");
-MODULE_LICENSE("GPL");
-MODULE_VERSION(DRIVER_VERSION);
+/* Temporary hack for merging atl1 and atl2 */
+#include "atlx.c"
/*
* atl1_pci_tbl - PCI Device ID Table
@@ -104,7 +99,6 @@ static const struct pci_device_id atl1_pci_tbl[] = {
/* required last entry */
{0,}
};
-
MODULE_DEVICE_TABLE(pci, atl1_pci_tbl);
/*
@@ -125,7 +119,7 @@ static int __devinit atl1_sw_init(struct atl1_adapter *adapter)
adapter->wol = 0;
adapter->rx_buffer_len = (hw->max_frame_size + 7) & ~7;
- adapter->ict = 50000; /* 100ms */
+ adapter->ict = 50000; /* 100ms */
adapter->link_speed = SPEED_0; /* hardware init */
adapter->link_duplex = FULL_DUPLEX;
@@ -206,24 +200,6 @@ static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
}
/*
- * atl1_ioctl -
- * @netdev:
- * @ifreq:
- * @cmd:
- */
-static int atl1_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
-{
- switch (cmd) {
- case SIOCGMIIPHY:
- case SIOCGMIIREG:
- case SIOCSMIIREG:
- return atl1_mii_ioctl(netdev, ifr, cmd);
- default:
- return -EOPNOTSUPP;
- }
-}
-
-/*
* atl1_setup_mem_resources - allocate Tx / RX descriptor resources
* @adapter: board private structure
*
@@ -248,7 +224,8 @@ s32 atl1_setup_ring_resources(struct atl1_adapter *adapter)
rfd_ring->buffer_info =
(struct atl1_buffer *)(tpd_ring->buffer_info + tpd_ring->count);
- /* real ring DMA buffer
+ /*
+ * real ring DMA buffer
* each ring/block may need up to 8 bytes for alignment, hence the
* additional 40 bytes tacked onto the end.
*/
@@ -307,7 +284,7 @@ s32 atl1_setup_ring_resources(struct atl1_adapter *adapter)
((u8 *) adapter->cmb.cmb +
(sizeof(struct coals_msg_block) + offset));
- return ATL1_SUCCESS;
+ return 0;
err_nomem:
kfree(tpd_ring->buffer_info);
@@ -481,31 +458,6 @@ static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter)
iowrite32(value, hw->hw_addr + REG_MAC_CTRL);
}
-/*
- * atl1_set_mac - Change the Ethernet Address of the NIC
- * @netdev: network interface device structure
- * @p: pointer to an address structure
- *
- * Returns 0 on success, negative on failure
- */
-static int atl1_set_mac(struct net_device *netdev, void *p)
-{
- struct atl1_adapter *adapter = netdev_priv(netdev);
- struct sockaddr *addr = p;
-
- if (netif_running(netdev))
- return -EBUSY;
-
- if (!is_valid_ether_addr(addr->sa_data))
- return -EADDRNOTAVAIL;
-
- memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
- memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
-
- atl1_set_mac_addr(&adapter->hw);
- return 0;
-}
-
static u32 atl1_check_link(struct atl1_adapter *adapter)
{
struct atl1_hw *hw = &adapter->hw;
@@ -517,14 +469,16 @@ static u32 atl1_check_link(struct atl1_adapter *adapter)
/* MII_BMSR must read twice */
atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
- if (!(phy_data & BMSR_LSTATUS)) { /* link down */
- if (netif_carrier_ok(netdev)) { /* old link state: Up */
+ if (!(phy_data & BMSR_LSTATUS)) {
+ /* link down */
+ if (netif_carrier_ok(netdev)) {
+ /* old link state: Up */
dev_info(&adapter->pdev->dev, "link is down\n");
adapter->link_speed = SPEED_0;
netif_carrier_off(netdev);
netif_stop_queue(netdev);
}
- return ATL1_SUCCESS;
+ return 0;
}
/* Link Up */
@@ -568,14 +522,15 @@ static u32 atl1_check_link(struct atl1_adapter *adapter)
adapter->link_duplex == FULL_DUPLEX ?
"full duplex" : "half duplex");
}
- if (!netif_carrier_ok(netdev)) { /* Link down -> Up */
+ if (!netif_carrier_ok(netdev)) {
+ /* Link down -> Up */
netif_carrier_on(netdev);
netif_wake_queue(netdev);
}
- return ATL1_SUCCESS;
+ return 0;
}
- /* change orignal link status */
+ /* change original link status */
if (netif_carrier_ok(netdev)) {
adapter->link_speed = SPEED_0;
netif_carrier_off(netdev);
@@ -596,12 +551,13 @@ static u32 atl1_check_link(struct atl1_adapter *adapter)
phy_data =
MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
break;
- default: /* MEDIA_TYPE_10M_HALF: */
+ default:
+ /* MEDIA_TYPE_10M_HALF: */
phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
break;
}
atl1_write_phy_reg(hw, MII_BMCR, phy_data);
- return ATL1_SUCCESS;
+ return 0;
}
/* auto-neg, insert timer to re-config phy */
@@ -610,71 +566,7 @@ static u32 atl1_check_link(struct atl1_adapter *adapter)
mod_timer(&adapter->phy_config_timer, jiffies + 3 * HZ);
}
- return ATL1_SUCCESS;
-}
-
-static void atl1_check_for_link(struct atl1_adapter *adapter)
-{
- struct net_device *netdev = adapter->netdev;
- u16 phy_data = 0;
-
- spin_lock(&adapter->lock);
- adapter->phy_timer_pending = false;
- atl1_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
- atl1_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
- spin_unlock(&adapter->lock);
-
- /* notify upper layer link down ASAP */
- if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */
- if (netif_carrier_ok(netdev)) { /* old link state: Up */
- dev_info(&adapter->pdev->dev, "%s link is down\n",
- netdev->name);
- adapter->link_speed = SPEED_0;
- netif_carrier_off(netdev);
- netif_stop_queue(netdev);
- }
- }
- schedule_work(&adapter->link_chg_task);
-}
-
-/*
- * atl1_set_multi - Multicast and Promiscuous mode set
- * @netdev: network interface device structure
- *
- * The set_multi entry point is called whenever the multicast address
- * list or the network interface flags are updated. This routine is
- * responsible for configuring the hardware for proper multicast,
- * promiscuous mode, and all-multi behavior.
- */
-static void atl1_set_multi(struct net_device *netdev)
-{
- struct atl1_adapter *adapter = netdev_priv(netdev);
- struct atl1_hw *hw = &adapter->hw;
- struct dev_mc_list *mc_ptr;
- u32 rctl;
- u32 hash_value;
-
- /* Check for Promiscuous and All Multicast modes */
- rctl = ioread32(hw->hw_addr + REG_MAC_CTRL);
- if (netdev->flags & IFF_PROMISC)
- rctl |= MAC_CTRL_PROMIS_EN;
- else if (netdev->flags & IFF_ALLMULTI) {
- rctl |= MAC_CTRL_MC_ALL_EN;
- rctl &= ~MAC_CTRL_PROMIS_EN;
- } else
- rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
-
- iowrite32(rctl, hw->hw_addr + REG_MAC_CTRL);
-
- /* clear the old settings from the multicast hash table */
- iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
- iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
-
- /* compute mc addresses' hash value ,and put it into hash table */
- for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
- hash_value = atl1_hash_mc_addr(hw, mc_ptr->dmi_addr);
- atl1_hash_set(hw, hash_value);
- }
+ return 0;
}
/*
@@ -974,37 +866,6 @@ static void atl1_via_workaround(struct atl1_adapter *adapter)
iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND);
}
-/*
- * atl1_irq_enable - Enable default interrupt generation settings
- * @adapter: board private structure
- */
-static void atl1_irq_enable(struct atl1_adapter *adapter)
-{
- iowrite32(IMR_NORMAL_MASK, adapter->hw.hw_addr + REG_IMR);
- ioread32(adapter->hw.hw_addr + REG_IMR);
-}
-
-/*
- * atl1_irq_disable - Mask off interrupt generation on the NIC
- * @adapter: board private structure
- */
-static void atl1_irq_disable(struct atl1_adapter *adapter)
-{
- iowrite32(0, adapter->hw.hw_addr + REG_IMR);
- ioread32(adapter->hw.hw_addr + REG_IMR);
- synchronize_irq(adapter->pdev->irq);
-}
-
-static void atl1_clear_phy_int(struct atl1_adapter *adapter)
-{
- u16 phy_data;
- unsigned long flags;
-
- spin_lock_irqsave(&adapter->lock, flags);
- atl1_read_phy_reg(&adapter->hw, 19, &phy_data);
- spin_unlock_irqrestore(&adapter->lock, flags);
-}
-
static void atl1_inc_smb(struct atl1_adapter *adapter)
{
struct stats_msg_block *smb = adapter->smb.smb;
@@ -1076,19 +937,6 @@ static void atl1_inc_smb(struct atl1_adapter *adapter)
adapter->soft_stats.tx_carrier_errors;
}
-/*
- * atl1_get_stats - Get System Network Statistics
- * @netdev: network interface device structure
- *
- * Returns the address of the device statistics structure.
- * The statistics are actually updated from the timer callback.
- */
-static struct net_device_stats *atl1_get_stats(struct net_device *netdev)
-{
- struct atl1_adapter *adapter = netdev_priv(netdev);
- return &adapter->net_stats;
-}
-
static void atl1_update_mailbox(struct atl1_adapter *adapter)
{
unsigned long flags;
@@ -1210,7 +1058,8 @@ static u16 atl1_alloc_rx_buffers(struct atl1_adapter *adapter)
rfd_desc = ATL1_RFD_DESC(rfd_ring, rfd_next_to_use);
skb = dev_alloc_skb(adapter->rx_buffer_len + NET_IP_ALIGN);
- if (unlikely(!skb)) { /* Better luck next round */
+ if (unlikely(!skb)) {
+ /* Better luck next round */
adapter->net_stats.rx_dropped++;
break;
}
@@ -1519,7 +1368,8 @@ static void atl1_tx_map(struct atl1_adapter *adapter, struct sk_buff *skb,
buffer_info = &tpd_ring->buffer_info[tpd_next_to_use];
if (unlikely(buffer_info->skb))
BUG();
- buffer_info->skb = NULL; /* put skb in last TPD */
+ /* put skb in last TPD */
+ buffer_info->skb = NULL;
if (tcp_seg) {
/* TSO/GSO */
@@ -1779,7 +1629,7 @@ static irqreturn_t atl1_intr(int irq, void *data)
adapter->cmb.cmb->int_stats = 0;
if (status & ISR_GPHY) /* clear phy status */
- atl1_clear_phy_int(adapter);
+ atlx_clear_phy_int(adapter);
/* clear ISR status, and Enable CMB DMA/Disable Interrupt */
iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR);
@@ -1866,23 +1716,12 @@ static void atl1_phy_config(unsigned long data)
spin_lock_irqsave(&adapter->lock, flags);
adapter->phy_timer_pending = false;
atl1_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
- atl1_write_phy_reg(hw, MII_AT001_CR, hw->mii_1000t_ctrl_reg);
+ atl1_write_phy_reg(hw, MII_ATLX_CR, hw->mii_1000t_ctrl_reg);
atl1_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN);
spin_unlock_irqrestore(&adapter->lock, flags);
}
/*
- * atl1_tx_timeout - Respond to a Tx Hang
- * @netdev: network interface device structure
- */
-static void atl1_tx_timeout(struct net_device *netdev)
-{
- struct atl1_adapter *adapter = netdev_priv(netdev);
- /* Do the reset outside of interrupt context */
- schedule_work(&adapter->tx_timeout_task);
-}
-
-/*
* Orphaned vendor comment left intact here:
* <vendor comment>
* If TPD Buffer size equal to 0, PCIE DMAR_TO_INT
@@ -1904,58 +1743,11 @@ static void atl1_tx_timeout_task(struct work_struct *work)
netif_device_attach(netdev);
}
-/*
- * atl1_link_chg_task - deal with link change event Out of interrupt context
- */
-static void atl1_link_chg_task(struct work_struct *work)
-{
- struct atl1_adapter *adapter =
- container_of(work, struct atl1_adapter, link_chg_task);
- unsigned long flags;
-
- spin_lock_irqsave(&adapter->lock, flags);
- atl1_check_link(adapter);
- spin_unlock_irqrestore(&adapter->lock, flags);
-}
-
-static void atl1_vlan_rx_register(struct net_device *netdev,
- struct vlan_group *grp)
-{
- struct atl1_adapter *adapter = netdev_priv(netdev);
- unsigned long flags;
- u32 ctrl;
-
- spin_lock_irqsave(&adapter->lock, flags);
- /* atl1_irq_disable(adapter); */
- adapter->vlgrp = grp;
-
- if (grp) {
- /* enable VLAN tag insert/strip */
- ctrl = ioread32(adapter->hw.hw_addr + REG_MAC_CTRL);
- ctrl |= MAC_CTRL_RMV_VLAN;
- iowrite32(ctrl, adapter->hw.hw_addr + REG_MAC_CTRL);
- } else {
- /* disable VLAN tag insert/strip */
- ctrl = ioread32(adapter->hw.hw_addr + REG_MAC_CTRL);
- ctrl &= ~MAC_CTRL_RMV_VLAN;
- iowrite32(ctrl, adapter->hw.hw_addr + REG_MAC_CTRL);
- }
-
- /* atl1_irq_enable(adapter); */
- spin_unlock_irqrestore(&adapter->lock, flags);
-}
-
-static void atl1_restore_vlan(struct atl1_adapter *adapter)
-{
- atl1_vlan_rx_register(adapter->netdev, adapter->vlgrp);
-}
-
int atl1_reset(struct atl1_adapter *adapter)
{
int ret;
-
ret = atl1_reset_hw(&adapter->hw);
- if (ret != ATL1_SUCCESS)
+ if (ret)
return ret;
return atl1_init_hw(&adapter->hw);
}
@@ -1967,11 +1759,12 @@ s32 atl1_up(struct atl1_adapter *adapter)
int irq_flags = IRQF_SAMPLE_RANDOM;
/* hardware has been reset, we need to reload some things */
- atl1_set_multi(netdev);
+ atlx_set_multi(netdev);
atl1_init_ring_ptrs(adapter);
- atl1_restore_vlan(adapter);
+ atlx_restore_vlan(adapter);
err = atl1_alloc_rx_buffers(adapter);
- if (unlikely(!err)) /* no RX BUFFER allocated */
+ if (unlikely(!err))
+ /* no RX BUFFER allocated */
return -ENOMEM;
if (unlikely(atl1_configure(adapter))) {
@@ -1992,7 +1785,7 @@ s32 atl1_up(struct atl1_adapter *adapter)
goto err_up;
mod_timer(&adapter->watchdog_timer, jiffies);
- atl1_irq_enable(adapter);
+ atlx_irq_enable(adapter);
atl1_check_link(adapter);
return 0;
@@ -2011,7 +1804,7 @@ void atl1_down(struct atl1_adapter *adapter)
del_timer_sync(&adapter->phy_config_timer);
adapter->phy_timer_pending = false;
- atl1_irq_disable(adapter);
+ atlx_irq_disable(adapter);
free_irq(adapter->pdev->irq, netdev);
pci_disable_msi(adapter->pdev);
atl1_reset_hw(&adapter->hw);
@@ -2094,7 +1887,7 @@ static int atl1_suspend(struct pci_dev *pdev, pm_message_t state)
atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
if (ctrl & BMSR_LSTATUS)
- wufc &= ~ATL1_WUFC_LNKC;
+ wufc &= ~ATLX_WUFC_LNKC;
/* reduce speed to 10/100M */
if (wufc) {
@@ -2102,15 +1895,15 @@ static int atl1_suspend(struct pci_dev *pdev, pm_message_t state)
/* if resume, let driver to re- setup link */
hw->phy_configured = false;
atl1_set_mac_addr(hw);
- atl1_set_multi(netdev);
+ atlx_set_multi(netdev);
ctrl = 0;
/* turn on magic packet wol */
- if (wufc & ATL1_WUFC_MAG)
+ if (wufc & ATLX_WUFC_MAG)
ctrl = WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
/* turn on Link change WOL */
- if (wufc & ATL1_WUFC_LNKC)
+ if (wufc & ATLX_WUFC_LNKC)
ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
@@ -2118,13 +1911,13 @@ static int atl1_suspend(struct pci_dev *pdev, pm_message_t state)
ctrl = ioread32(hw->hw_addr + REG_MAC_CTRL);
ctrl &= ~MAC_CTRL_DBG;
ctrl &= ~MAC_CTRL_PROMIS_EN;
- if (wufc & ATL1_WUFC_MC)
+ if (wufc & ATLX_WUFC_MC)
ctrl |= MAC_CTRL_MC_ALL_EN;
else
ctrl &= ~MAC_CTRL_MC_ALL_EN;
/* turn on broadcast mode if wake on-BC is enabled */
- if (wufc & ATL1_WUFC_BC)
+ if (wufc & ATLX_WUFC_BC)
ctrl |= MAC_CTRL_BC_EN;
else
ctrl &= ~MAC_CTRL_BC_EN;
@@ -2152,12 +1945,13 @@ static int atl1_resume(struct pci_dev *pdev)
{
struct net_device *netdev = pci_get_drvdata(pdev);
struct atl1_adapter *adapter = netdev_priv(netdev);
- u32 ret_val;
+ u32 err;
- pci_set_power_state(pdev, 0);
+ pci_set_power_state(pdev, PCI_D0);
pci_restore_state(pdev);
- ret_val = pci_enable_device(pdev);
+ /* FIXME: check and handle */
+ err = pci_enable_device(pdev);
pci_enable_wake(pdev, PCI_D3hot, 0);
pci_enable_wake(pdev, PCI_D3cold, 0);
@@ -2224,14 +2018,16 @@ static int __devinit atl1_probe(struct pci_dev *pdev,
dev_err(&pdev->dev, "no usable DMA configuration\n");
goto err_dma;
}
- /* Mark all PCI regions associated with PCI device
+ /*
+ * Mark all PCI regions associated with PCI device
* pdev as being reserved by owner atl1_driver_name
*/
- err = pci_request_regions(pdev, atl1_driver_name);
+ err = pci_request_regions(pdev, ATLX_DRIVER_NAME);
if (err)
goto err_request_regions;
- /* Enables bus-mastering on the device and calls
+ /*
+ * Enables bus-mastering on the device and calls
* pcibios_set_master to do the needed arch specific settings
*/
pci_set_master(pdev);
@@ -2257,7 +2053,7 @@ static int __devinit atl1_probe(struct pci_dev *pdev,
/* get device revision number */
adapter->hw.dev_rev = ioread16(adapter->hw.hw_addr +
(REG_MASTER_CTRL + 2));
- dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
+ dev_info(&pdev->dev, "version %s\n", ATLX_DRIVER_VERSION);
/* set default ring resource counts */
adapter->rfd_ring.count = adapter->rrd_ring.count = ATL1_DEFAULT_RFD;
@@ -2272,17 +2068,17 @@ static int __devinit atl1_probe(struct pci_dev *pdev,
netdev->open = &atl1_open;
netdev->stop = &atl1_close;
netdev->hard_start_xmit = &atl1_xmit_frame;
- netdev->get_stats = &atl1_get_stats;
- netdev->set_multicast_list = &atl1_set_multi;
+ netdev->get_stats = &atlx_get_stats;
+ netdev->set_multicast_list = &atlx_set_multi;
netdev->set_mac_address = &atl1_set_mac;
netdev->change_mtu = &atl1_change_mtu;
- netdev->do_ioctl = &atl1_ioctl;
- netdev->tx_timeout = &atl1_tx_timeout;
+ netdev->do_ioctl = &atlx_ioctl;
+ netdev->tx_timeout = &atlx_tx_timeout;
netdev->watchdog_timeo = 5 * HZ;
#ifdef CONFIG_NET_POLL_CONTROLLER
netdev->poll_controller = atl1_poll_controller;
#endif
- netdev->vlan_rx_register = atl1_vlan_rx_register;
+ netdev->vlan_rx_register = atlx_vlan_rx_register;
netdev->ethtool_ops = &atl1_ethtool_ops;
adapter->bd_number = cards_found;
@@ -2312,7 +2108,7 @@ static int __devinit atl1_probe(struct pci_dev *pdev,
/* atl1_pcie_patch(adapter); */
/* really reset GPHY core */
- iowrite16(0, adapter->hw.hw_addr + REG_GPHY_ENABLE);
+ iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
/*
* reset the controller to
@@ -2357,7 +2153,7 @@ static int __devinit atl1_probe(struct pci_dev *pdev,
INIT_WORK(&adapter->tx_timeout_task, atl1_tx_timeout_task);
- INIT_WORK(&adapter->link_chg_task, atl1_link_chg_task);
+ INIT_WORK(&adapter->link_chg_task, atlx_link_chg_task);
INIT_WORK(&adapter->pcie_dma_to_rst_task, atl1_tx_timeout_task);
@@ -2400,7 +2196,8 @@ static void __devexit atl1_remove(struct pci_dev *pdev)
adapter = netdev_priv(netdev);
- /* Some atl1 boards lack persistent storage for their MAC, and get it
+ /*
+ * Some atl1 boards lack persistent storage for their MAC, and get it
* from the BIOS during POST. If we've been messing with the MAC
* address, we need to save the permanent one.
*/
@@ -2410,7 +2207,7 @@ static void __devexit atl1_remove(struct pci_dev *pdev)
atl1_set_mac_addr(&adapter->hw);
}
- iowrite16(0, adapter->hw.hw_addr + REG_GPHY_ENABLE);
+ iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
unregister_netdev(netdev);
pci_iounmap(pdev, adapter->hw.hw_addr);
pci_release_regions(pdev);
@@ -2419,7 +2216,7 @@ static void __devexit atl1_remove(struct pci_dev *pdev)
}
static struct pci_driver atl1_driver = {
- .name = atl1_driver_name,
+ .name = ATLX_DRIVER_NAME,
.id_table = atl1_pci_tbl,
.probe = atl1_probe,
.remove = __devexit_p(atl1_remove),
@@ -2451,3 +2248,1170 @@ static int __init atl1_init_module(void)
module_init(atl1_init_module);
module_exit(atl1_exit_module);
+
+struct atl1_stats {
+ char stat_string[ETH_GSTRING_LEN];
+ int sizeof_stat;
+ int stat_offset;
+};
+
+#define ATL1_STAT(m) \
+ sizeof(((struct atl1_adapter *)0)->m), offsetof(struct atl1_adapter, m)
+
+static struct atl1_stats atl1_gstrings_stats[] = {
+ {"rx_packets", ATL1_STAT(soft_stats.rx_packets)},
+ {"tx_packets", ATL1_STAT(soft_stats.tx_packets)},
+ {"rx_bytes", ATL1_STAT(soft_stats.rx_bytes)},
+ {"tx_bytes", ATL1_STAT(soft_stats.tx_bytes)},
+ {"rx_errors", ATL1_STAT(soft_stats.rx_errors)},
+ {"tx_errors", ATL1_STAT(soft_stats.tx_errors)},
+ {"rx_dropped", ATL1_STAT(net_stats.rx_dropped)},
+ {"tx_dropped", ATL1_STAT(net_stats.tx_dropped)},
+ {"multicast", ATL1_STAT(soft_stats.multicast)},
+ {"collisions", ATL1_STAT(soft_stats.collisions)},
+ {"rx_length_errors", ATL1_STAT(soft_stats.rx_length_errors)},
+ {"rx_over_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
+ {"rx_crc_errors", ATL1_STAT(soft_stats.rx_crc_errors)},
+ {"rx_frame_errors", ATL1_STAT(soft_stats.rx_frame_errors)},
+ {"rx_fifo_errors", ATL1_STAT(soft_stats.rx_fifo_errors)},
+ {"rx_missed_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
+ {"tx_aborted_errors", ATL1_STAT(soft_stats.tx_aborted_errors)},
+ {"tx_carrier_errors", ATL1_STAT(soft_stats.tx_carrier_errors)},
+ {"tx_fifo_errors", ATL1_STAT(soft_stats.tx_fifo_errors)},
+ {"tx_window_errors", ATL1_STAT(soft_stats.tx_window_errors)},
+ {"tx_abort_exce_coll", ATL1_STAT(soft_stats.excecol)},
+ {"tx_abort_late_coll", ATL1_STAT(soft_stats.latecol)},
+ {"tx_deferred_ok", ATL1_STAT(soft_stats.deffer)},
+ {"tx_single_coll_ok", ATL1_STAT(soft_stats.scc)},
+ {"tx_multi_coll_ok", ATL1_STAT(soft_stats.mcc)},
+ {"tx_underun", ATL1_STAT(soft_stats.tx_underun)},
+ {"tx_trunc", ATL1_STAT(soft_stats.tx_trunc)},
+ {"tx_pause", ATL1_STAT(soft_stats.tx_pause)},
+ {"rx_pause", ATL1_STAT(soft_stats.rx_pause)},
+ {"rx_rrd_ov", ATL1_STAT(soft_stats.rx_rrd_ov)},
+ {"rx_trunc", ATL1_STAT(soft_stats.rx_trunc)}
+};
+
+static void atl1_get_ethtool_stats(struct net_device *netdev,
+ struct ethtool_stats *stats, u64 *data)
+{
+ struct atl1_adapter *adapter = netdev_priv(netdev);
+ int i;
+ char *p;
+
+ for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
+ p = (char *)adapter+atl1_gstrings_stats[i].stat_offset;
+ data[i] = (atl1_gstrings_stats[i].sizeof_stat ==
+ sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
+ }
+
+}
+
+static int atl1_get_sset_count(struct net_device *netdev, int sset)
+{
+ switch (sset) {
+ case ETH_SS_STATS:
+ return ARRAY_SIZE(atl1_gstrings_stats);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int atl1_get_settings(struct net_device *netdev,
+ struct ethtool_cmd *ecmd)
+{
+ struct atl1_adapter *adapter = netdev_priv(netdev);
+ struct atl1_hw *hw = &adapter->hw;
+
+ ecmd->supported = (SUPPORTED_10baseT_Half |
+ SUPPORTED_10baseT_Full |
+ SUPPORTED_100baseT_Half |
+ SUPPORTED_100baseT_Full |
+ SUPPORTED_1000baseT_Full |
+ SUPPORTED_Autoneg | SUPPORTED_TP);
+ ecmd->advertising = ADVERTISED_TP;
+ if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
+ hw->media_type == MEDIA_TYPE_1000M_FULL) {
+ ecmd->advertising |= ADVERTISED_Autoneg;
+ if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR) {
+ ecmd->advertising |= ADVERTISED_Autoneg;
+ ecmd->advertising |=
+ (ADVERTISED_10baseT_Half |
+ ADVERTISED_10baseT_Full |
+ ADVERTISED_100baseT_Half |
+ ADVERTISED_100baseT_Full |
+ ADVERTISED_1000baseT_Full);
+ } else
+ ecmd->advertising |= (ADVERTISED_1000baseT_Full);
+ }
+ ecmd->port = PORT_TP;
+ ecmd->phy_address = 0;
+ ecmd->transceiver = XCVR_INTERNAL;
+
+ if (netif_carrier_ok(adapter->netdev)) {
+ u16 link_speed, link_duplex;
+ atl1_get_speed_and_duplex(hw, &link_speed, &link_duplex);
+ ecmd->speed = link_speed;
+ if (link_duplex == FULL_DUPLEX)
+ ecmd->duplex = DUPLEX_FULL;
+ else
+ ecmd->duplex = DUPLEX_HALF;
+ } else {
+ ecmd->speed = -1;
+ ecmd->duplex = -1;
+ }
+ if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
+ hw->media_type == MEDIA_TYPE_1000M_FULL)
+ ecmd->autoneg = AUTONEG_ENABLE;
+ else
+ ecmd->autoneg = AUTONEG_DISABLE;
+
+ return 0;
+}
+
+static int atl1_set_settings(struct net_device *netdev,
+ struct ethtool_cmd *ecmd)
+{
+ struct atl1_adapter *adapter = netdev_priv(netdev);
+ struct atl1_hw *hw = &adapter->hw;
+ u16 phy_data;
+ int ret_val = 0;
+ u16 old_media_type = hw->media_type;
+
+ if (netif_running(adapter->netdev)) {
+ dev_dbg(&adapter->pdev->dev, "ethtool shutting down adapter\n");
+ atl1_down(adapter);
+ }
+
+ if (ecmd->autoneg == AUTONEG_ENABLE)
+ hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
+ else {
+ if (ecmd->speed == SPEED_1000) {
+ if (ecmd->duplex != DUPLEX_FULL) {
+ dev_warn(&adapter->pdev->dev,
+ "can't force to 1000M half duplex\n");
+ ret_val = -EINVAL;
+ goto exit_sset;
+ }
+ hw->media_type = MEDIA_TYPE_1000M_FULL;
+ } else if (ecmd->speed == SPEED_100) {
+ if (ecmd->duplex == DUPLEX_FULL)
+ hw->media_type = MEDIA_TYPE_100M_FULL;
+ else
+ hw->media_type = MEDIA_TYPE_100M_HALF;
+ } else {
+ if (ecmd->duplex == DUPLEX_FULL)
+ hw->media_type = MEDIA_TYPE_10M_FULL;
+ else
+ hw->media_type = MEDIA_TYPE_10M_HALF;
+ }
+ }
+ switch (hw->media_type) {
+ case MEDIA_TYPE_AUTO_SENSOR:
+ ecmd->advertising =
+ ADVERTISED_10baseT_Half |
+ ADVERTISED_10baseT_Full |
+ ADVERTISED_100baseT_Half |
+ ADVERTISED_100baseT_Full |
+ ADVERTISED_1000baseT_Full |
+ ADVERTISED_Autoneg | ADVERTISED_TP;
+ break;
+ case MEDIA_TYPE_1000M_FULL:
+ ecmd->advertising =
+ ADVERTISED_1000baseT_Full |
+ ADVERTISED_Autoneg | ADVERTISED_TP;
+ break;
+ default:
+ ecmd->advertising = 0;
+ break;
+ }
+ if (atl1_phy_setup_autoneg_adv(hw)) {
+ ret_val = -EINVAL;
+ dev_warn(&adapter->pdev->dev,
+ "invalid ethtool speed/duplex setting\n");
+ goto exit_sset;
+ }
+ if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
+ hw->media_type == MEDIA_TYPE_1000M_FULL)
+ phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
+ else {
+ switch (hw->media_type) {
+ case MEDIA_TYPE_100M_FULL:
+ phy_data =
+ MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
+ MII_CR_RESET;
+ break;
+ case MEDIA_TYPE_100M_HALF:
+ phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
+ break;
+ case MEDIA_TYPE_10M_FULL:
+ phy_data =
+ MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
+ break;
+ default:
+ /* MEDIA_TYPE_10M_HALF: */
+ phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
+ break;
+ }
+ }
+ atl1_write_phy_reg(hw, MII_BMCR, phy_data);
+exit_sset:
+ if (ret_val)
+ hw->media_type = old_media_type;
+
+ if (netif_running(adapter->netdev)) {
+ dev_dbg(&adapter->pdev->dev, "ethtool starting adapter\n");
+ atl1_up(adapter);
+ } else if (!ret_val) {
+ dev_dbg(&adapter->pdev->dev, "ethtool resetting adapter\n");
+ atl1_reset(adapter);
+ }
+ return ret_val;
+}
+
+static void atl1_get_drvinfo(struct net_device *netdev,
+ struct ethtool_drvinfo *drvinfo)
+{
+ struct atl1_adapter *adapter = netdev_priv(netdev);
+
+ strncpy(drvinfo->driver, ATLX_DRIVER_NAME, sizeof(drvinfo->driver));
+ strncpy(drvinfo->version, ATLX_DRIVER_VERSION,
+ sizeof(drvinfo->version));
+ strncpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
+ strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
+ sizeof(drvinfo->bus_info));
+ drvinfo->eedump_len = ATL1_EEDUMP_LEN;
+}
+
+static void atl1_get_wol(struct net_device *netdev,
+ struct ethtool_wolinfo *wol)
+{
+ struct atl1_adapter *adapter = netdev_priv(netdev);
+
+ wol->supported = WAKE_UCAST | WAKE_MCAST | WAKE_BCAST | WAKE_MAGIC;
+ wol->wolopts = 0;
+ if (adapter->wol & ATLX_WUFC_EX)
+ wol->wolopts |= WAKE_UCAST;
+ if (adapter->wol & ATLX_WUFC_MC)
+ wol->wolopts |= WAKE_MCAST;
+ if (adapter->wol & ATLX_WUFC_BC)
+ wol->wolopts |= WAKE_BCAST;
+ if (adapter->wol & ATLX_WUFC_MAG)
+ wol->wolopts |= WAKE_MAGIC;
+ return;
+}
+
+static int atl1_set_wol(struct net_device *netdev,
+ struct ethtool_wolinfo *wol)
+{
+ struct atl1_adapter *adapter = netdev_priv(netdev);
+
+ if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
+ return -EOPNOTSUPP;
+ adapter->wol = 0;
+ if (wol->wolopts & WAKE_UCAST)
+ adapter->wol |= ATLX_WUFC_EX;
+ if (wol->wolopts & WAKE_MCAST)
+ adapter->wol |= ATLX_WUFC_MC;
+ if (wol->wolopts & WAKE_BCAST)
+ adapter->wol |= ATLX_WUFC_BC;
+ if (wol->wolopts & WAKE_MAGIC)
+ adapter->wol |= ATLX_WUFC_MAG;
+ return 0;
+}
+
+static void atl1_get_ringparam(struct net_device *netdev,
+ struct ethtool_ringparam *ring)
+{
+ struct atl1_adapter *adapter = netdev_priv(netdev);
+ struct atl1_tpd_ring *txdr = &adapter->tpd_ring;
+ struct atl1_rfd_ring *rxdr = &adapter->rfd_ring;
+
+ ring->rx_max_pending = ATL1_MAX_RFD;
+ ring->tx_max_pending = ATL1_MAX_TPD;
+ ring->rx_mini_max_pending = 0;
+ ring->rx_jumbo_max_pending = 0;
+ ring->rx_pending = rxdr->count;
+ ring->tx_pending = txdr->count;
+ ring->rx_mini_pending = 0;
+ ring->rx_jumbo_pending = 0;
+}
+
+static int atl1_set_ringparam(struct net_device *netdev,
+ struct ethtool_ringparam *ring)
+{
+ struct atl1_adapter *adapter = netdev_priv(netdev);
+ struct atl1_tpd_ring *tpdr = &adapter->tpd_ring;
+ struct atl1_rrd_ring *rrdr = &adapter->rrd_ring;
+ struct atl1_rfd_ring *rfdr = &adapter->rfd_ring;
+
+ struct atl1_tpd_ring tpd_old, tpd_new;
+ struct atl1_rfd_ring rfd_old, rfd_new;
+ struct atl1_rrd_ring rrd_old, rrd_new;
+ struct atl1_ring_header rhdr_old, rhdr_new;
+ int err;
+
+ tpd_old = adapter->tpd_ring;
+ rfd_old = adapter->rfd_ring;
+ rrd_old = adapter->rrd_ring;
+ rhdr_old = adapter->ring_header;
+
+ if (netif_running(adapter->netdev))
+ atl1_down(adapter);
+
+ rfdr->count = (u16) max(ring->rx_pending, (u32) ATL1_MIN_RFD);
+ rfdr->count = rfdr->count > ATL1_MAX_RFD ? ATL1_MAX_RFD :
+ rfdr->count;
+ rfdr->count = (rfdr->count + 3) & ~3;
+ rrdr->count = rfdr->count;
+
+ tpdr->count = (u16) max(ring->tx_pending, (u32) ATL1_MIN_TPD);
+ tpdr->count = tpdr->count > ATL1_MAX_TPD ? ATL1_MAX_TPD :
+ tpdr->count;
+ tpdr->count = (tpdr->count + 3) & ~3;
+
+ if (netif_running(adapter->netdev)) {
+ /* try to get new resources before deleting old */
+ err = atl1_setup_ring_resources(adapter);
+ if (err)
+ goto err_setup_ring;
+
+ /*
+ * save the new, restore the old in order to free it,
+ * then restore the new back again
+ */
+
+ rfd_new = adapter->rfd_ring;
+ rrd_new = adapter->rrd_ring;
+ tpd_new = adapter->tpd_ring;
+ rhdr_new = adapter->ring_header;
+ adapter->rfd_ring = rfd_old;
+ adapter->rrd_ring = rrd_old;
+ adapter->tpd_ring = tpd_old;
+ adapter->ring_header = rhdr_old;
+ atl1_free_ring_resources(adapter);
+ adapter->rfd_ring = rfd_new;
+ adapter->rrd_ring = rrd_new;
+ adapter->tpd_ring = tpd_new;
+ adapter->ring_header = rhdr_new;
+
+ err = atl1_up(adapter);
+ if (err)
+ return err;
+ }
+ return 0;
+
+err_setup_ring:
+ adapter->rfd_ring = rfd_old;
+ adapter->rrd_ring = rrd_old;
+ adapter->tpd_ring = tpd_old;
+ adapter->ring_header = rhdr_old;
+ atl1_up(adapter);
+ return err;
+}
+
+static void atl1_get_pauseparam(struct net_device *netdev,
+ struct ethtool_pauseparam *epause)
+{
+ struct atl1_adapter *adapter = netdev_priv(netdev);
+ struct atl1_hw *hw = &adapter->hw;
+
+ if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
+ hw->media_type == MEDIA_TYPE_1000M_FULL) {
+ epause->autoneg = AUTONEG_ENABLE;
+ } else {
+ epause->autoneg = AUTONEG_DISABLE;
+ }
+ epause->rx_pause = 1;
+ epause->tx_pause = 1;
+}
+
+static int atl1_set_pauseparam(struct net_device *netdev,
+ struct ethtool_pauseparam *epause)
+{
+ struct atl1_adapter *adapter = netdev_priv(netdev);
+ struct atl1_hw *hw = &adapter->hw;
+
+ if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
+ hw->media_type == MEDIA_TYPE_1000M_FULL) {
+ epause->autoneg = AUTONEG_ENABLE;
+ } else {
+ epause->autoneg = AUTONEG_DISABLE;
+ }
+
+ epause->rx_pause = 1;
+ epause->tx_pause = 1;
+
+ return 0;
+}
+
+/* FIXME: is this right? -- CHS */
+static u32 atl1_get_rx_csum(struct net_device *netdev)
+{
+ return 1;
+}
+
+static void atl1_get_strings(struct net_device *netdev, u32 stringset,
+ u8 *data)
+{
+ u8 *p = data;
+ int i;
+
+ switch (stringset) {
+ case ETH_SS_STATS:
+ for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
+ memcpy(p, atl1_gstrings_stats[i].stat_string,
+ ETH_GSTRING_LEN);
+ p += ETH_GSTRING_LEN;
+ }
+ break;
+ }
+}
+
+static int atl1_nway_reset(struct net_device *netdev)
+{
+ struct atl1_adapter *adapter = netdev_priv(netdev);
+ struct atl1_hw *hw = &adapter->hw;
+
+ if (netif_running(netdev)) {
+ u16 phy_data;
+ atl1_down(adapter);
+
+ if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
+ hw->media_type == MEDIA_TYPE_1000M_FULL) {
+ phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
+ } else {
+ switch (hw->media_type) {
+ case MEDIA_TYPE_100M_FULL:
+ phy_data = MII_CR_FULL_DUPLEX |
+ MII_CR_SPEED_100 | MII_CR_RESET;
+ break;
+ case MEDIA_TYPE_100M_HALF:
+ phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
+ break;
+ case MEDIA_TYPE_10M_FULL:
+ phy_data = MII_CR_FULL_DUPLEX |
+ MII_CR_SPEED_10 | MII_CR_RESET;
+ break;
+ default:
+ /* MEDIA_TYPE_10M_HALF */
+ phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
+ }
+ }
+ atl1_write_phy_reg(hw, MII_BMCR, phy_data);
+ atl1_up(adapter);
+ }
+ return 0;
+}
+
+const struct ethtool_ops atl1_ethtool_ops = {
+ .get_settings = atl1_get_settings,
+ .set_settings = atl1_set_settings,
+ .get_drvinfo = atl1_get_drvinfo,
+ .get_wol = atl1_get_wol,
+ .set_wol = atl1_set_wol,
+ .get_ringparam = atl1_get_ringparam,
+ .set_ringparam = atl1_set_ringparam,
+ .get_pauseparam = atl1_get_pauseparam,
+ .set_pauseparam = atl1_set_pauseparam,
+ .get_rx_csum = atl1_get_rx_csum,
+ .set_tx_csum = ethtool_op_set_tx_hw_csum,
+ .get_link = ethtool_op_get_link,
+ .set_sg = ethtool_op_set_sg,
+ .get_strings = atl1_get_strings,
+ .nway_reset = atl1_nway_reset,
+ .get_ethtool_stats = atl1_get_ethtool_stats,
+ .get_sset_count = atl1_get_sset_count,
+ .set_tso = ethtool_op_set_tso,
+};
+
+/*
+ * Reset the transmit and receive units; mask and clear all interrupts.
+ * hw - Struct containing variables accessed by shared code
+ * return : 0 or idle status (if error)
+ */
+s32 atl1_reset_hw(struct atl1_hw *hw)
+{
+ struct pci_dev *pdev = hw->back->pdev;
+ u32 icr;
+ int i;
+
+ /*
+ * Clear Interrupt mask to stop board from generating
+ * interrupts & Clear any pending interrupt events
+ */
+ /*
+ * iowrite32(0, hw->hw_addr + REG_IMR);
+ * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
+ */
+
+ /*
+ * Issue Soft Reset to the MAC. This will reset the chip's
+ * transmit, receive, DMA. It will not effect
+ * the current PCI configuration. The global reset bit is self-
+ * clearing, and should clear within a microsecond.
+ */
+ iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
+ ioread32(hw->hw_addr + REG_MASTER_CTRL);
+
+ iowrite16(1, hw->hw_addr + REG_PHY_ENABLE);
+ ioread16(hw->hw_addr + REG_PHY_ENABLE);
+
+ /* delay about 1ms */
+ msleep(1);
+
+ /* Wait at least 10ms for All module to be Idle */
+ for (i = 0; i < 10; i++) {
+ icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
+ if (!icr)
+ break;
+ /* delay 1 ms */
+ msleep(1);
+ /* FIXME: still the right way to do this? */
+ cpu_relax();
+ }
+
+ if (icr) {
+ dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr);
+ return icr;
+ }
+
+ return 0;
+}
+
+/* function about EEPROM
+ *
+ * check_eeprom_exist
+ * return 0 if eeprom exist
+ */
+static int atl1_check_eeprom_exist(struct atl1_hw *hw)
+{
+ u32 value;
+ value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
+ if (value & SPI_FLASH_CTRL_EN_VPD) {
+ value &= ~SPI_FLASH_CTRL_EN_VPD;
+ iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
+ }
+
+ value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
+ return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
+}
+
+static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
+{
+ int i;
+ u32 control;
+
+ if (offset & 3)
+ /* address do not align */
+ return false;
+
+ iowrite32(0, hw->hw_addr + REG_VPD_DATA);
+ control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
+ iowrite32(control, hw->hw_addr + REG_VPD_CAP);
+ ioread32(hw->hw_addr + REG_VPD_CAP);
+
+ for (i = 0; i < 10; i++) {
+ msleep(2);
+ control = ioread32(hw->hw_addr + REG_VPD_CAP);
+ if (control & VPD_CAP_VPD_FLAG)
+ break;
+ }
+ if (control & VPD_CAP_VPD_FLAG) {
+ *p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
+ return true;
+ }
+ /* timeout */
+ return false;
+}
+
+/*
+ * Reads the value from a PHY register
+ * hw - Struct containing variables accessed by shared code
+ * reg_addr - address of the PHY register to read
+ */
+s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
+{
+ u32 val;
+ int i;
+
+ val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
+ MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
+ MDIO_CLK_SEL_SHIFT;
+ iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
+ ioread32(hw->hw_addr + REG_MDIO_CTRL);
+
+ for (i = 0; i < MDIO_WAIT_TIMES; i++) {
+ udelay(2);
+ val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
+ if (!(val & (MDIO_START | MDIO_BUSY)))
+ break;
+ }
+ if (!(val & (MDIO_START | MDIO_BUSY))) {
+ *phy_data = (u16) val;
+ return 0;
+ }
+ return ATLX_ERR_PHY;
+}
+
+#define CUSTOM_SPI_CS_SETUP 2
+#define CUSTOM_SPI_CLK_HI 2
+#define CUSTOM_SPI_CLK_LO 2
+#define CUSTOM_SPI_CS_HOLD 2
+#define CUSTOM_SPI_CS_HI 3
+
+static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
+{
+ int i;
+ u32 value;
+
+ iowrite32(0, hw->hw_addr + REG_SPI_DATA);
+ iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
+
+ value = SPI_FLASH_CTRL_WAIT_READY |
+ (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
+ SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
+ SPI_FLASH_CTRL_CLK_HI_MASK) <<
+ SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
+ SPI_FLASH_CTRL_CLK_LO_MASK) <<
+ SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
+ SPI_FLASH_CTRL_CS_HOLD_MASK) <<
+ SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
+ SPI_FLASH_CTRL_CS_HI_MASK) <<
+ SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
+ SPI_FLASH_CTRL_INS_SHIFT;
+
+ iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
+
+ value |= SPI_FLASH_CTRL_START;
+ iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
+ ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
+
+ for (i = 0; i < 10; i++) {
+ msleep(1);
+ value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
+ if (!(value & SPI_FLASH_CTRL_START))
+ break;
+ }
+
+ if (value & SPI_FLASH_CTRL_START)
+ return false;
+
+ *buf = ioread32(hw->hw_addr + REG_SPI_DATA);
+
+ return true;
+}
+
+/*
+ * get_permanent_address
+ * return 0 if get valid mac address,
+ */
+static int atl1_get_permanent_address(struct atl1_hw *hw)
+{
+ u32 addr[2];
+ u32 i, control;
+ u16 reg;
+ u8 eth_addr[ETH_ALEN];
+ bool key_valid;
+
+ if (is_valid_ether_addr(hw->perm_mac_addr))
+ return 0;
+
+ /* init */
+ addr[0] = addr[1] = 0;
+
+ if (!atl1_check_eeprom_exist(hw)) {
+ reg = 0;
+ key_valid = false;
+ /* Read out all EEPROM content */
+ i = 0;
+ while (1) {
+ if (atl1_read_eeprom(hw, i + 0x100, &control)) {
+ if (key_valid) {
+ if (reg == REG_MAC_STA_ADDR)
+ addr[0] = control;
+ else if (reg == (REG_MAC_STA_ADDR + 4))
+ addr[1] = control;
+ key_valid = false;
+ } else if ((control & 0xff) == 0x5A) {
+ key_valid = true;
+ reg = (u16) (control >> 16);
+ } else
+ break;
+ } else
+ /* read error */
+ break;
+ i += 4;
+ }
+
+ *(u32 *) ð_addr[2] = swab32(addr[0]);
+ *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]);
+ if (is_valid_ether_addr(eth_addr)) {
+ memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
+ return 0;
+ }
+ return 1;
+ }
+
+ /* see if SPI FLAGS exist ? */
+ addr[0] = addr[1] = 0;
+ reg = 0;
+ key_valid = false;
+ i = 0;
+ while (1) {
+ if (atl1_spi_read(hw, i + 0x1f000, &control)) {
+ if (key_valid) {
+ if (reg == REG_MAC_STA_ADDR)
+ addr[0] = control;
+ else if (reg == (REG_MAC_STA_ADDR + 4))
+ addr[1] = control;
+ key_valid = false;
+ } else if ((control & 0xff) == 0x5A) {
+ key_valid = true;
+ reg = (u16) (control >> 16);
+ } else
+ /* data end */
+ break;
+ } else
+ /* read error */
+ break;
+ i += 4;
+ }
+
+ *(u32 *) ð_addr[2] = swab32(addr[0]);
+ *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]);
+ if (is_valid_ether_addr(eth_addr)) {
+ memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
+ return 0;
+ }
+
+ /*
+ * On some motherboards, the MAC address is written by the
+ * BIOS directly to the MAC register during POST, and is
+ * not stored in eeprom. If all else thus far has failed
+ * to fetch the permanent MAC address, try reading it directly.
+ */
+ addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
+ addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
+ *(u32 *) ð_addr[2] = swab32(addr[0]);
+ *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]);
+ if (is_valid_ether_addr(eth_addr)) {
+ memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
+ return 0;
+ }
+
+ return 1;
+}
+
+/*
+ * Reads the adapter's MAC address from the EEPROM
+ * hw - Struct containing variables accessed by shared code
+ */
+s32 atl1_read_mac_addr(struct atl1_hw *hw)
+{
+ u16 i;
+
+ if (atl1_get_permanent_address(hw))
+ random_ether_addr(hw->perm_mac_addr);
+
+ for (i = 0; i < ETH_ALEN; i++)
+ hw->mac_addr[i] = hw->perm_mac_addr[i];
+ return 0;
+}
+
+/*
+ * Hashes an address to determine its location in the multicast table
+ * hw - Struct containing variables accessed by shared code
+ * mc_addr - the multicast address to hash
+ *
+ * atl1_hash_mc_addr
+ * purpose
+ * set hash value for a multicast address
+ * hash calcu processing :
+ * 1. calcu 32bit CRC for multicast address
+ * 2. reverse crc with MSB to LSB
+ */
+u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
+{
+ u32 crc32, value = 0;
+ int i;
+
+ crc32 = ether_crc_le(6, mc_addr);
+ for (i = 0; i < 32; i++)
+ value |= (((crc32 >> i) & 1) << (31 - i));
+
+ return value;
+}
+
+/*
+ * Sets the bit in the multicast table corresponding to the hash value.
+ * hw - Struct containing variables accessed by shared code
+ * hash_value - Multicast address hash value
+ */
+void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
+{
+ u32 hash_bit, hash_reg;
+ u32 mta;
+
+ /*
+ * The HASH Table is a register array of 2 32-bit registers.
+ * It is treated like an array of 64 bits. We want to set
+ * bit BitArray[hash_value]. So we figure out what register
+ * the bit is in, read it, OR in the new bit, then write
+ * back the new value. The register is determined by the
+ * upper 7 bits of the hash value and the bit within that
+ * register are determined by the lower 5 bits of the value.
+ */
+ hash_reg = (hash_value >> 31) & 0x1;
+ hash_bit = (hash_value >> 26) & 0x1F;
+ mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
+ mta |= (1 << hash_bit);
+ iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
+}
+
+/*
+ * Writes a value to a PHY register
+ * hw - Struct containing variables accessed by shared code
+ * reg_addr - address of the PHY register to write
+ * data - data to write to the PHY
+ */
+s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
+{
+ int i;
+ u32 val;
+
+ val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
+ (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
+ MDIO_SUP_PREAMBLE |
+ MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
+ iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
+ ioread32(hw->hw_addr + REG_MDIO_CTRL);
+
+ for (i = 0; i < MDIO_WAIT_TIMES; i++) {
+ udelay(2);
+ val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
+ if (!(val & (MDIO_START | MDIO_BUSY)))
+ break;
+ }
+
+ if (!(val & (MDIO_START | MDIO_BUSY)))
+ return 0;
+
+ return ATLX_ERR_PHY;
+}
+
+/*
+ * Make L001's PHY out of Power Saving State (bug)
+ * hw - Struct containing variables accessed by shared code
+ * when power on, L001's PHY always on Power saving State
+ * (Gigabit Link forbidden)
+ */
+static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
+{
+ s32 ret;
+ ret = atl1_write_phy_reg(hw, 29, 0x0029);
+ if (ret)
+ return ret;
+ return atl1_write_phy_reg(hw, 30, 0);
+}
+
+/*
+ *TODO: do something or get rid of this
+ */
+s32 atl1_phy_enter_power_saving(struct atl1_hw *hw)
+{
+/* s32 ret_val;
+ * u16 phy_data;
+ */
+
+/*
+ ret_val = atl1_write_phy_reg(hw, ...);
+ ret_val = atl1_write_phy_reg(hw, ...);
+ ....
+*/
+ return 0;
+}
+
+/*
+ * Resets the PHY and make all config validate
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
+ */
+static s32 atl1_phy_reset(struct atl1_hw *hw)
+{
+ struct pci_dev *pdev = hw->back->pdev;
+ s32 ret_val;
+ u16 phy_data;
+
+ if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
+ hw->media_type == MEDIA_TYPE_1000M_FULL)
+ phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
+ else {
+ switch (hw->media_type) {
+ case MEDIA_TYPE_100M_FULL:
+ phy_data =
+ MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
+ MII_CR_RESET;
+ break;
+ case MEDIA_TYPE_100M_HALF:
+ phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
+ break;
+ case MEDIA_TYPE_10M_FULL:
+ phy_data =
+ MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
+ break;
+ default:
+ /* MEDIA_TYPE_10M_HALF: */
+ phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
+ break;
+ }
+ }
+
+ ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
+ if (ret_val) {
+ u32 val;
+ int i;
+ /* pcie serdes link may be down! */
+ dev_dbg(&pdev->dev, "pcie phy link down\n");
+
+ for (i = 0; i < 25; i++) {
+ msleep(1);
+ val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
+ if (!(val & (MDIO_START | MDIO_BUSY)))
+ break;
+ }
+
+ if ((val & (MDIO_START | MDIO_BUSY)) != 0) {
+ dev_warn(&pdev->dev, "pcie link down at least 25ms\n");
+ return ret_val;
+ }
+ }
+ return 0;
+}
+
+/*
+ * Configures PHY autoneg and flow control advertisement settings
+ * hw - Struct containing variables accessed by shared code
+ */
+s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
+{
+ s32 ret_val;
+ s16 mii_autoneg_adv_reg;
+ s16 mii_1000t_ctrl_reg;
+
+ /* Read the MII Auto-Neg Advertisement Register (Address 4). */
+ mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
+
+ /* Read the MII 1000Base-T Control Register (Address 9). */
+ mii_1000t_ctrl_reg = MII_ATLX_CR_1000T_DEFAULT_CAP_MASK;
+
+ /*
+ * First we clear all the 10/100 mb speed bits in the Auto-Neg
+ * Advertisement Register (Address 4) and the 1000 mb speed bits in
+ * the 1000Base-T Control Register (Address 9).
+ */
+ mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
+ mii_1000t_ctrl_reg &= ~MII_ATLX_CR_1000T_SPEED_MASK;
+
+ /*
+ * Need to parse media_type and set up
+ * the appropriate PHY registers.
+ */
+ switch (hw->media_type) {
+ case MEDIA_TYPE_AUTO_SENSOR:
+ mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
+ MII_AR_10T_FD_CAPS |
+ MII_AR_100TX_HD_CAPS |
+ MII_AR_100TX_FD_CAPS);
+ mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
+ break;
+
+ case MEDIA_TYPE_1000M_FULL:
+ mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
+ break;
+
+ case MEDIA_TYPE_100M_FULL:
+ mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
+ break;
+
+ case MEDIA_TYPE_100M_HALF:
+ mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
+ break;
+
+ case MEDIA_TYPE_10M_FULL:
+ mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
+ break;
+
+ default:
+ mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
+ break;
+ }
+
+ /* flow control fixed to enable all */
+ mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
+
+ hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
+ hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
+
+ ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
+ if (ret_val)
+ return ret_val;
+
+ ret_val = atl1_write_phy_reg(hw, MII_ATLX_CR, mii_1000t_ctrl_reg);
+ if (ret_val)
+ return ret_val;
+
+ return 0;
+}
+
+/*
+ * Configures link settings.
+ * hw - Struct containing variables accessed by shared code
+ * Assumes the hardware has previously been reset and the
+ * transmitter and receiver are not enabled.
+ */
+static s32 atl1_setup_link(struct atl1_hw *hw)
+{
+ struct pci_dev *pdev = hw->back->pdev;
+ s32 ret_val;
+
+ /*
+ * Options:
+ * PHY will advertise value(s) parsed from
+ * autoneg_advertised and fc
+ * no matter what autoneg is , We will not wait link result.
+ */
+ ret_val = atl1_phy_setup_autoneg_adv(hw);
+ if (ret_val) {
+ dev_dbg(&pdev->dev, "error setting up autonegotiation\n");
+ return ret_val;
+ }
+ /* SW.Reset , En-Auto-Neg if needed */
+ ret_val = atl1_phy_reset(hw);
+ if (ret_val) {
+ dev_dbg(&pdev->dev, "error resetting phy\n");
+ return ret_val;
+ }
+ hw->phy_configured = true;
+ return ret_val;
+}
+
+static void atl1_init_flash_opcode(struct atl1_hw *hw)
+{
+ if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
+ /* Atmel */
+ hw->flash_vendor = 0;
+
+ /* Init OP table */
+ iowrite8(flash_table[hw->flash_vendor].cmd_program,
+ hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
+ iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
+ hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
+ iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
+ hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
+ iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
+ hw->hw_addr + REG_SPI_FLASH_OP_RDID);
+ iowrite8(flash_table[hw->flash_vendor].cmd_wren,
+ hw->hw_addr + REG_SPI_FLASH_OP_WREN);
+ iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
+ hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
+ iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
+ hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
+ iowrite8(flash_table[hw->flash_vendor].cmd_read,
+ hw->hw_addr + REG_SPI_FLASH_OP_READ);
+}
+
+/*
+ * Performs basic configuration of the adapter.
+ * hw - Struct containing variables accessed by shared code
+ * Assumes that the controller has previously been reset and is in a
+ * post-reset uninitialized state. Initializes multicast table,
+ * and Calls routines to setup link
+ * Leaves the transmit and receive units disabled and uninitialized.
+ */
+s32 atl1_init_hw(struct atl1_hw *hw)
+{
+ u32 ret_val = 0;
+
+ /* Zero out the Multicast HASH table */
+ iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
+ /* clear the old settings from the multicast hash table */
+ iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
+
+ atl1_init_flash_opcode(hw);
+
+ if (!hw->phy_configured) {
+ /* enable GPHY LinkChange Interrrupt */
+ ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
+ if (ret_val)
+ return ret_val;
+ /* make PHY out of power-saving state */
+ ret_val = atl1_phy_leave_power_saving(hw);
+ if (ret_val)
+ return ret_val;
+ /* Call a subroutine to configure the link */
+ ret_val = atl1_setup_link(hw);
+ }
+ return ret_val;
+}
+
+/*
+ * Detects the current speed and duplex settings of the hardware.
+ * hw - Struct containing variables accessed by shared code
+ * speed - Speed of the connection
+ * duplex - Duplex setting of the connection
+ */
+s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
+{
+ struct pci_dev *pdev = hw->back->pdev;
+ s32 ret_val;
+ u16 phy_data;
+
+ /* ; --- Read PHY Specific Status Register (17) */
+ ret_val = atl1_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
+ if (ret_val)
+ return ret_val;
+
+ if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
+ return ATLX_ERR_PHY_RES;
+
+ switch (phy_data & MII_ATLX_PSSR_SPEED) {
+ case MII_ATLX_PSSR_1000MBS:
+ *speed = SPEED_1000;
+ break;
+ case MII_ATLX_PSSR_100MBS:
+ *speed = SPEED_100;
+ break;
+ case MII_ATLX_PSSR_10MBS:
+ *speed = SPEED_10;
+ break;
+ default:
+ dev_dbg(&pdev->dev, "error getting speed\n");
+ return ATLX_ERR_PHY_SPEED;
+ break;
+ }
+ if (phy_data & MII_ATLX_PSSR_DPLX)
+ *duplex = FULL_DUPLEX;
+ else
+ *duplex = HALF_DUPLEX;
+
+ return 0;
+}
+
+void atl1_set_mac_addr(struct atl1_hw *hw)
+{
+ u32 value;
+ /*
+ * 00-0B-6A-F6-00-DC
+ * 0: 6AF600DC 1: 000B
+ * low dword
+ */
+ value = (((u32) hw->mac_addr[2]) << 24) |
+ (((u32) hw->mac_addr[3]) << 16) |
+ (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
+ iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
+ /* high dword */
+ value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
+ iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
+}
diff --git a/drivers/net/atlx/atl1.h b/drivers/net/atlx/atl1.h
index ff4765f..538948d 100644
--- a/drivers/net/atlx/atl1.h
+++ b/drivers/net/atlx/atl1.h
@@ -1,6 +1,6 @@
/*
* Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
- * Copyright(c) 2006 Chris Snook <csnook@redhat.com>
+ * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
* Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
*
* Derived from Intel e1000 driver
@@ -21,26 +21,559 @@
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
-#ifndef _ATL1_H_
-#define _ATL1_H_
+#ifndef ATL1_H
+#define ATL1_H
-#include <linux/types.h>
+#include <linux/compiler.h>
+#include <linux/ethtool.h>
#include <linux/if_vlan.h>
+#include <linux/mii.h>
+#include <linux/module.h>
+#include <linux/skbuff.h>
+#include <linux/spinlock.h>
+#include <linux/timer.h>
+#include <linux/types.h>
+#include <linux/workqueue.h>
+
+#include "atlx.h"
+
+#define ATLX_DRIVER_NAME "atl1"
-#include "atl1_hw.h"
+MODULE_DESCRIPTION("Atheros L1 Gigabit Ethernet Driver");
+
+#define atlx_adapter atl1_adapter
+#define atlx_check_for_link atl1_check_for_link
+#define atlx_check_link atl1_check_link
+#define atlx_hash_mc_addr atl1_hash_mc_addr
+#define atlx_hash_set atl1_hash_set
+#define atlx_hw atl1_hw
+#define atlx_mii_ioctl atl1_mii_ioctl
+#define atlx_read_phy_reg atl1_read_phy_reg
+#define atlx_set_mac atl1_set_mac
+#define atlx_set_mac_addr atl1_set_mac_addr
+
+struct atl1_adapter;
+struct atl1_hw;
/* function prototypes needed by multiple files */
+s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw);
+s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data);
+s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex);
+s32 atl1_read_mac_addr(struct atl1_hw *hw);
+s32 atl1_init_hw(struct atl1_hw *hw);
+s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex);
+s32 atl1_set_speed_and_duplex(struct atl1_hw *hw, u16 speed, u16 duplex);
+u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr);
+void atl1_hash_set(struct atl1_hw *hw, u32 hash_value);
+s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data);
+void atl1_set_mac_addr(struct atl1_hw *hw);
+s32 atl1_phy_enter_power_saving(struct atl1_hw *hw);
+s32 atl1_reset_hw(struct atl1_hw *hw);
+void atl1_check_options(struct atl1_adapter *adapter);
+static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
+ int cmd);
+static u32 atl1_check_link(struct atl1_adapter *adapter);
s32 atl1_up(struct atl1_adapter *adapter);
void atl1_down(struct atl1_adapter *adapter);
int atl1_reset(struct atl1_adapter *adapter);
-s32 atl1_setup_ring_resources(struct atl1_adapter *adapter);
-void atl1_free_ring_resources(struct atl1_adapter *adapter);
-extern char atl1_driver_name[];
-extern char atl1_driver_version[];
extern const struct ethtool_ops atl1_ethtool_ops;
-struct atl1_adapter;
+/* hardware definitions specific to L1 */
+
+/* Block IDLE Status Register */
+#define IDLE_STATUS_RXMAC 0x1
+#define IDLE_STATUS_TXMAC 0x2
+#define IDLE_STATUS_RXQ 0x4
+#define IDLE_STATUS_TXQ 0x8
+#define IDLE_STATUS_DMAR 0x10
+#define IDLE_STATUS_DMAW 0x20
+#define IDLE_STATUS_SMB 0x40
+#define IDLE_STATUS_CMB 0x80
+
+/* MDIO Control Register */
+#define MDIO_WAIT_TIMES 30
+
+/* MAC Control Register */
+#define MAC_CTRL_TX_PAUSE 0x10000
+#define MAC_CTRL_SCNT 0x20000
+#define MAC_CTRL_SRST_TX 0x40000
+#define MAC_CTRL_TX_SIMURST 0x80000
+#define MAC_CTRL_SPEED_SHIFT 20
+#define MAC_CTRL_SPEED_MASK 0x300000
+#define MAC_CTRL_SPEED_1000 0x2
+#define MAC_CTRL_SPEED_10_100 0x1
+#define MAC_CTRL_DBG_TX_BKPRESURE 0x400000
+#define MAC_CTRL_TX_HUGE 0x800000
+#define MAC_CTRL_RX_CHKSUM_EN 0x1000000
+#define MAC_CTRL_DBG 0x8000000
+
+/* Wake-On-Lan control register */
+#define WOL_CLK_SWITCH_EN 0x8000
+#define WOL_PT5_EN 0x200000
+#define WOL_PT6_EN 0x400000
+#define WOL_PT5_MATCH 0x8000000
+#define WOL_PT6_MATCH 0x10000000
+
+/* WOL Length ( 2 DWORD ) */
+#define REG_WOL_PATTERN_LEN 0x14A4
+#define WOL_PT_LEN_MASK 0x7F
+#define WOL_PT0_LEN_SHIFT 0
+#define WOL_PT1_LEN_SHIFT 8
+#define WOL_PT2_LEN_SHIFT 16
+#define WOL_PT3_LEN_SHIFT 24
+#define WOL_PT4_LEN_SHIFT 0
+#define WOL_PT5_LEN_SHIFT 8
+#define WOL_PT6_LEN_SHIFT 16
+
+/* Internal SRAM Partition Registers, low 32 bits */
+#define REG_SRAM_RFD_LEN 0x1504
+#define REG_SRAM_RRD_ADDR 0x1508
+#define REG_SRAM_RRD_LEN 0x150C
+#define REG_SRAM_TPD_ADDR 0x1510
+#define REG_SRAM_TPD_LEN 0x1514
+#define REG_SRAM_TRD_ADDR 0x1518
+#define REG_SRAM_TRD_LEN 0x151C
+#define REG_SRAM_RXF_ADDR 0x1520
+#define REG_SRAM_RXF_LEN 0x1524
+#define REG_SRAM_TXF_ADDR 0x1528
+#define REG_SRAM_TXF_LEN 0x152C
+#define REG_SRAM_TCPH_PATH_ADDR 0x1530
+#define SRAM_TCPH_ADDR_MASK 0xFFF
+#define SRAM_TCPH_ADDR_SHIFT 0
+#define SRAM_PATH_ADDR_MASK 0xFFF
+#define SRAM_PATH_ADDR_SHIFT 16
+
+/* Load Ptr Register */
+#define REG_LOAD_PTR 0x1534
+
+/* Descriptor Control registers, low 32 bits */
+#define REG_DESC_RFD_ADDR_LO 0x1544
+#define REG_DESC_RRD_ADDR_LO 0x1548
+#define REG_DESC_TPD_ADDR_LO 0x154C
+#define REG_DESC_CMB_ADDR_LO 0x1550
+#define REG_DESC_SMB_ADDR_LO 0x1554
+#define REG_DESC_RFD_RRD_RING_SIZE 0x1558
+#define DESC_RFD_RING_SIZE_MASK 0x7FF
+#define DESC_RFD_RING_SIZE_SHIFT 0
+#define DESC_RRD_RING_SIZE_MASK 0x7FF
+#define DESC_RRD_RING_SIZE_SHIFT 16
+#define REG_DESC_TPD_RING_SIZE 0x155C
+#define DESC_TPD_RING_SIZE_MASK 0x3FF
+#define DESC_TPD_RING_SIZE_SHIFT 0
+
+/* TXQ Control Register */
+#define REG_TXQ_CTRL 0x1580
+#define TXQ_CTRL_TPD_BURST_NUM_SHIFT 0
+#define TXQ_CTRL_TPD_BURST_NUM_MASK 0x1F
+#define TXQ_CTRL_EN 0x20
+#define TXQ_CTRL_ENH_MODE 0x40
+#define TXQ_CTRL_TPD_FETCH_TH_SHIFT 8
+#define TXQ_CTRL_TPD_FETCH_TH_MASK 0x3F
+#define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16
+#define TXQ_CTRL_TXF_BURST_NUM_MASK 0xFFFF
+
+/* Jumbo packet Threshold for task offload */
+#define REG_TX_JUMBO_TASK_TH_TPD_IPG 0x1584
+#define TX_JUMBO_TASK_TH_MASK 0x7FF
+#define TX_JUMBO_TASK_TH_SHIFT 0
+#define TX_TPD_MIN_IPG_MASK 0x1F
+#define TX_TPD_MIN_IPG_SHIFT 16
+
+/* RXQ Control Register */
+#define REG_RXQ_CTRL 0x15A0
+#define RXQ_CTRL_RFD_BURST_NUM_SHIFT 0
+#define RXQ_CTRL_RFD_BURST_NUM_MASK 0xFF
+#define RXQ_CTRL_RRD_BURST_THRESH_SHIFT 8
+#define RXQ_CTRL_RRD_BURST_THRESH_MASK 0xFF
+#define RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT 16
+#define RXQ_CTRL_RFD_PREF_MIN_IPG_MASK 0x1F
+#define RXQ_CTRL_CUT_THRU_EN 0x40000000
+#define RXQ_CTRL_EN 0x80000000
+
+/* Rx jumbo packet threshold and rrd retirement timer */
+#define REG_RXQ_JMBOSZ_RRDTIM 0x15A4
+#define RXQ_JMBOSZ_TH_MASK 0x7FF
+#define RXQ_JMBOSZ_TH_SHIFT 0
+#define RXQ_JMBO_LKAH_MASK 0xF
+#define RXQ_JMBO_LKAH_SHIFT 11
+#define RXQ_RRD_TIMER_MASK 0xFFFF
+#define RXQ_RRD_TIMER_SHIFT 16
+
+/* RFD flow control register */
+#define REG_RXQ_RXF_PAUSE_THRESH 0x15A8
+#define RXQ_RXF_PAUSE_TH_HI_SHIFT 16
+#define RXQ_RXF_PAUSE_TH_HI_MASK 0xFFF
+#define RXQ_RXF_PAUSE_TH_LO_SHIFT 0
+#define RXQ_RXF_PAUSE_TH_LO_MASK 0xFFF
+
+/* RRD flow control register */
+#define REG_RXQ_RRD_PAUSE_THRESH 0x15AC
+#define RXQ_RRD_PAUSE_TH_HI_SHIFT 0
+#define RXQ_RRD_PAUSE_TH_HI_MASK 0xFFF
+#define RXQ_RRD_PAUSE_TH_LO_SHIFT 16
+#define RXQ_RRD_PAUSE_TH_LO_MASK 0xFFF
+
+/* DMA Engine Control Register */
+#define REG_DMA_CTRL 0x15C0
+#define DMA_CTRL_DMAR_IN_ORDER 0x1
+#define DMA_CTRL_DMAR_ENH_ORDER 0x2
+#define DMA_CTRL_DMAR_OUT_ORDER 0x4
+#define DMA_CTRL_RCB_VALUE 0x8
+#define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
+#define DMA_CTRL_DMAR_BURST_LEN_MASK 7
+#define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
+#define DMA_CTRL_DMAW_BURST_LEN_MASK 7
+#define DMA_CTRL_DMAR_EN 0x400
+#define DMA_CTRL_DMAW_EN 0x800
+
+/* CMB/SMB Control Register */
+#define REG_CSMB_CTRL 0x15D0
+#define CSMB_CTRL_CMB_NOW 1
+#define CSMB_CTRL_SMB_NOW 2
+#define CSMB_CTRL_CMB_EN 4
+#define CSMB_CTRL_SMB_EN 8
+
+/* CMB DMA Write Threshold Register */
+#define REG_CMB_WRITE_TH 0x15D4
+#define CMB_RRD_TH_SHIFT 0
+#define CMB_RRD_TH_MASK 0x7FF
+#define CMB_TPD_TH_SHIFT 16
+#define CMB_TPD_TH_MASK 0x7FF
+
+/* RX/TX count-down timer to trigger CMB-write. 2us resolution. */
+#define REG_CMB_WRITE_TIMER 0x15D8
+#define CMB_RX_TM_SHIFT 0
+#define CMB_RX_TM_MASK 0xFFFF
+#define CMB_TX_TM_SHIFT 16
+#define CMB_TX_TM_MASK 0xFFFF
+
+/* Number of packet received since last CMB write */
+#define REG_CMB_RX_PKT_CNT 0x15DC
+
+/* Number of packet transmitted since last CMB write */
+#define REG_CMB_TX_PKT_CNT 0x15E0
+
+/* SMB auto DMA timer register */
+#define REG_SMB_TIMER 0x15E4
+
+/* Mailbox Register */
+#define REG_MAILBOX 0x15F0
+#define MB_RFD_PROD_INDX_SHIFT 0
+#define MB_RFD_PROD_INDX_MASK 0x7FF
+#define MB_RRD_CONS_INDX_SHIFT 11
+#define MB_RRD_CONS_INDX_MASK 0x7FF
+#define MB_TPD_PROD_INDX_SHIFT 22
+#define MB_TPD_PROD_INDX_MASK 0x3FF
+
+/* Interrupt Status Register */
+#define ISR_SMB 0x1
+#define ISR_TIMER 0x2
+#define ISR_MANUAL 0x4
+#define ISR_RXF_OV 0x8
+#define ISR_RFD_UNRUN 0x10
+#define ISR_RRD_OV 0x20
+#define ISR_TXF_UNRUN 0x40
+#define ISR_LINK 0x80
+#define ISR_HOST_RFD_UNRUN 0x100
+#define ISR_HOST_RRD_OV 0x200
+#define ISR_DMAR_TO_RST 0x400
+#define ISR_DMAW_TO_RST 0x800
+#define ISR_GPHY 0x1000
+#define ISR_RX_PKT 0x10000
+#define ISR_TX_PKT 0x20000
+#define ISR_TX_DMA 0x40000
+#define ISR_RX_DMA 0x80000
+#define ISR_CMB_RX 0x100000
+#define ISR_CMB_TX 0x200000
+#define ISR_MAC_RX 0x400000
+#define ISR_MAC_TX 0x800000
+#define ISR_DIS_SMB 0x20000000
+#define ISR_DIS_DMA 0x40000000
+
+/* Normal Interrupt mask */
+#define IMR_NORMAL_MASK (\
+ ISR_SMB |\
+ ISR_GPHY |\
+ ISR_PHY_LINKDOWN|\
+ ISR_DMAR_TO_RST |\
+ ISR_DMAW_TO_RST |\
+ ISR_CMB_TX |\
+ ISR_CMB_RX)
+
+/* Debug Interrupt Mask (enable all interrupt) */
+#define IMR_DEBUG_MASK (\
+ ISR_SMB |\
+ ISR_TIMER |\
+ ISR_MANUAL |\
+ ISR_RXF_OV |\
+ ISR_RFD_UNRUN |\
+ ISR_RRD_OV |\
+ ISR_TXF_UNRUN |\
+ ISR_LINK |\
+ ISR_CMB_TX |\
+ ISR_CMB_RX |\
+ ISR_RX_PKT |\
+ ISR_TX_PKT |\
+ ISR_MAC_RX |\
+ ISR_MAC_TX)
+
+#define MEDIA_TYPE_1000M_FULL 1
+#define MEDIA_TYPE_100M_FULL 2
+#define MEDIA_TYPE_100M_HALF 3
+#define MEDIA_TYPE_10M_FULL 4
+#define MEDIA_TYPE_10M_HALF 5
+
+#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* All but 1000-Half */
+
+#define MAX_JUMBO_FRAME_SIZE 10240
+
+#define ATL1_EEDUMP_LEN 48
+
+/* Statistics counters collected by the MAC */
+struct stats_msg_block {
+ /* rx */
+ u32 rx_ok; /* good RX packets */
+ u32 rx_bcast; /* good RX broadcast packets */
+ u32 rx_mcast; /* good RX multicast packets */
+ u32 rx_pause; /* RX pause frames */
+ u32 rx_ctrl; /* RX control packets other than pause frames */
+ u32 rx_fcs_err; /* RX packets with bad FCS */
+ u32 rx_len_err; /* RX packets with length != actual size */
+ u32 rx_byte_cnt; /* good bytes received. FCS is NOT included */
+ u32 rx_runt; /* RX packets < 64 bytes with good FCS */
+ u32 rx_frag; /* RX packets < 64 bytes with bad FCS */
+ u32 rx_sz_64; /* 64 byte RX packets */
+ u32 rx_sz_65_127;
+ u32 rx_sz_128_255;
+ u32 rx_sz_256_511;
+ u32 rx_sz_512_1023;
+ u32 rx_sz_1024_1518;
+ u32 rx_sz_1519_max; /* 1519 byte to MTU RX packets */
+ u32 rx_sz_ov; /* truncated RX packets > MTU */
+ u32 rx_rxf_ov; /* frames dropped due to RX FIFO overflow */
+ u32 rx_rrd_ov; /* frames dropped due to RRD overflow */
+ u32 rx_align_err; /* alignment errors */
+ u32 rx_bcast_byte_cnt; /* RX broadcast bytes, excluding FCS */
+ u32 rx_mcast_byte_cnt; /* RX multicast bytes, excluding FCS */
+ u32 rx_err_addr; /* packets dropped due to address filtering */
+
+ /* tx */
+ u32 tx_ok; /* good TX packets */
+ u32 tx_bcast; /* good TX broadcast packets */
+ u32 tx_mcast; /* good TX multicast packets */
+ u32 tx_pause; /* TX pause frames */
+ u32 tx_exc_defer; /* TX packets deferred excessively */
+ u32 tx_ctrl; /* TX control frames, excluding pause frames */
+ u32 tx_defer; /* TX packets deferred */
+ u32 tx_byte_cnt; /* bytes transmitted, FCS is NOT included */
+ u32 tx_sz_64; /* 64 byte TX packets */
+ u32 tx_sz_65_127;
+ u32 tx_sz_128_255;
+ u32 tx_sz_256_511;
+ u32 tx_sz_512_1023;
+ u32 tx_sz_1024_1518;
+ u32 tx_sz_1519_max; /* 1519 byte to MTU TX packets */
+ u32 tx_1_col; /* packets TX after a single collision */
+ u32 tx_2_col; /* packets TX after multiple collisions */
+ u32 tx_late_col; /* TX packets with late collisions */
+ u32 tx_abort_col; /* TX packets aborted w/excessive collisions */
+ u32 tx_underrun; /* TX packets aborted due to TX FIFO underrun
+ * or TRD FIFO underrun */
+ u32 tx_rd_eop; /* reads beyond the EOP into the next frame
+ * when TRD was not written timely */
+ u32 tx_len_err; /* TX packets where length != actual size */
+ u32 tx_trunc; /* TX packets truncated due to size > MTU */
+ u32 tx_bcast_byte; /* broadcast bytes transmitted, excluding FCS */
+ u32 tx_mcast_byte; /* multicast bytes transmitted, excluding FCS */
+ u32 smb_updated; /* 1: SMB Updated. This is used by software to
+ * indicate the statistics update. Software
+ * should clear this bit after retrieving the
+ * statistics information. */
+};
+
+/* Coalescing Message Block */
+struct coals_msg_block {
+ u32 int_stats; /* interrupt status */
+ u16 rrd_prod_idx; /* TRD Producer Index. */
+ u16 rfd_cons_idx; /* RFD Consumer Index. */
+ u16 update; /* Selene sets this bit every time it DMAs the
+ * CMB to host memory. Software should clear
+ * this bit when CMB info is processed. */
+ u16 tpd_cons_idx; /* TPD Consumer Index. */
+};
+
+/* RRD descriptor */
+struct rx_return_desc {
+ u8 num_buf; /* Number of RFD buffers used by the received packet */
+ u8 resved;
+ u16 buf_indx; /* RFD Index of the first buffer */
+ union {
+ u32 valid;
+ struct {
+ u16 rx_chksum;
+ u16 pkt_size;
+ } xsum_sz;
+ } xsz;
+
+ u16 pkt_flg; /* Packet flags */
+ u16 err_flg; /* Error flags */
+ u16 resved2;
+ u16 vlan_tag; /* VLAN TAG */
+};
+
+#define PACKET_FLAG_ETH_TYPE 0x0080
+#define PACKET_FLAG_VLAN_INS 0x0100
+#define PACKET_FLAG_ERR 0x0200
+#define PACKET_FLAG_IPV4 0x0400
+#define PACKET_FLAG_UDP 0x0800
+#define PACKET_FLAG_TCP 0x1000
+#define PACKET_FLAG_BCAST 0x2000
+#define PACKET_FLAG_MCAST 0x4000
+#define PACKET_FLAG_PAUSE 0x8000
+
+#define ERR_FLAG_CRC 0x0001
+#define ERR_FLAG_CODE 0x0002
+#define ERR_FLAG_DRIBBLE 0x0004
+#define ERR_FLAG_RUNT 0x0008
+#define ERR_FLAG_OV 0x0010
+#define ERR_FLAG_TRUNC 0x0020
+#define ERR_FLAG_IP_CHKSUM 0x0040
+#define ERR_FLAG_L4_CHKSUM 0x0080
+#define ERR_FLAG_LEN 0x0100
+#define ERR_FLAG_DES_ADDR 0x0200
+
+/* RFD descriptor */
+struct rx_free_desc {
+ __le64 buffer_addr; /* Address of the descriptor's data buffer */
+ __le16 buf_len; /* Size of the receive buffer in host memory */
+ u16 coalese; /* Update consumer index to host after the
+ * reception of this frame */
+ /* __attribute__ ((packed)) is required */
+} __attribute__ ((packed));
+
+/* tsopu defines */
+#define TSO_PARAM_BUFLEN_MASK 0x3FFF
+#define TSO_PARAM_BUFLEN_SHIFT 0
+#define TSO_PARAM_DMAINT_MASK 0x0001
+#define TSO_PARAM_DMAINT_SHIFT 14
+#define TSO_PARAM_PKTNT_MASK 0x0001
+#define TSO_PARAM_PKTINT_SHIFT 15
+#define TSO_PARAM_VLANTAG_MASK 0xFFFF
+#define TSO_PARAM_VLAN_SHIFT 16
+
+/* tsopl defines */
+#define TSO_PARAM_EOP_MASK 0x0001
+#define TSO_PARAM_EOP_SHIFT 0
+#define TSO_PARAM_COALESCE_MASK 0x0001
+#define TSO_PARAM_COALESCE_SHIFT 1
+#define TSO_PARAM_INSVLAG_MASK 0x0001
+#define TSO_PARAM_INSVLAG_SHIFT 2
+#define TSO_PARAM_CUSTOMCKSUM_MASK 0x0001
+#define TSO_PARAM_CUSTOMCKSUM_SHIFT 3
+#define TSO_PARAM_SEGMENT_MASK 0x0001
+#define TSO_PARAM_SEGMENT_SHIFT 4
+#define TSO_PARAM_IPCKSUM_MASK 0x0001
+#define TSO_PARAM_IPCKSUM_SHIFT 5
+#define TSO_PARAM_TCPCKSUM_MASK 0x0001
+#define TSO_PARAM_TCPCKSUM_SHIFT 6
+#define TSO_PARAM_UDPCKSUM_MASK 0x0001
+#define TSO_PARAM_UDPCKSUM_SHIFT 7
+#define TSO_PARAM_VLANTAGGED_MASK 0x0001
+#define TSO_PARAM_VLANTAGGED_SHIFT 8
+#define TSO_PARAM_ETHTYPE_MASK 0x0001
+#define TSO_PARAM_ETHTYPE_SHIFT 9
+#define TSO_PARAM_IPHL_MASK 0x000F
+#define TSO_PARAM_IPHL_SHIFT 10
+#define TSO_PARAM_TCPHDRLEN_MASK 0x000F
+#define TSO_PARAM_TCPHDRLEN_SHIFT 14
+#define TSO_PARAM_HDRFLAG_MASK 0x0001
+#define TSO_PARAM_HDRFLAG_SHIFT 18
+#define TSO_PARAM_MSS_MASK 0x1FFF
+#define TSO_PARAM_MSS_SHIFT 19
+
+/* csumpu defines */
+#define CSUM_PARAM_BUFLEN_MASK 0x3FFF
+#define CSUM_PARAM_BUFLEN_SHIFT 0
+#define CSUM_PARAM_DMAINT_MASK 0x0001
+#define CSUM_PARAM_DMAINT_SHIFT 14
+#define CSUM_PARAM_PKTINT_MASK 0x0001
+#define CSUM_PARAM_PKTINT_SHIFT 15
+#define CSUM_PARAM_VALANTAG_MASK 0xFFFF
+#define CSUM_PARAM_VALAN_SHIFT 16
+
+/* csumpl defines*/
+#define CSUM_PARAM_EOP_MASK 0x0001
+#define CSUM_PARAM_EOP_SHIFT 0
+#define CSUM_PARAM_COALESCE_MASK 0x0001
+#define CSUM_PARAM_COALESCE_SHIFT 1
+#define CSUM_PARAM_INSVLAG_MASK 0x0001
+#define CSUM_PARAM_INSVLAG_SHIFT 2
+#define CSUM_PARAM_CUSTOMCKSUM_MASK 0x0001
+#define CSUM_PARAM_CUSTOMCKSUM_SHIFT 3
+#define CSUM_PARAM_SEGMENT_MASK 0x0001
+#define CSUM_PARAM_SEGMENT_SHIFT 4
+#define CSUM_PARAM_IPCKSUM_MASK 0x0001
+#define CSUM_PARAM_IPCKSUM_SHIFT 5
+#define CSUM_PARAM_TCPCKSUM_MASK 0x0001
+#define CSUM_PARAM_TCPCKSUM_SHIFT 6
+#define CSUM_PARAM_UDPCKSUM_MASK 0x0001
+#define CSUM_PARAM_UDPCKSUM_SHIFT 7
+#define CSUM_PARAM_VLANTAGGED_MASK 0x0001
+#define CSUM_PARAM_VLANTAGGED_SHIFT 8
+#define CSUM_PARAM_ETHTYPE_MASK 0x0001
+#define CSUM_PARAM_ETHTYPE_SHIFT 9
+#define CSUM_PARAM_IPHL_MASK 0x000F
+#define CSUM_PARAM_IPHL_SHIFT 10
+#define CSUM_PARAM_PLOADOFFSET_MASK 0x00FF
+#define CSUM_PARAM_PLOADOFFSET_SHIFT 16
+#define CSUM_PARAM_XSUMOFFSET_MASK 0x00FF
+#define CSUM_PARAM_XSUMOFFSET_SHIFT 24
+
+/* TPD descriptor */
+struct tso_param {
+ /* The order of these declarations is important -- don't change it */
+ u32 tsopu; /* tso_param upper word */
+ u32 tsopl; /* tso_param lower word */
+};
+
+struct csum_param {
+ /* The order of these declarations is important -- don't change it */
+ u32 csumpu; /* csum_param upper word */
+ u32 csumpl; /* csum_param lower word */
+};
+
+union tpd_descr {
+ u64 data;
+ struct csum_param csum;
+ struct tso_param tso;
+};
+
+struct tx_packet_desc {
+ __le64 buffer_addr;
+ union tpd_descr desc;
+};
+
+/* DMA Order Settings */
+enum atl1_dma_order {
+ atl1_dma_ord_in = 1,
+ atl1_dma_ord_enh = 2,
+ atl1_dma_ord_out = 4
+};
+
+enum atl1_dma_rcb {
+ atl1_rcb_64 = 0,
+ atl1_rcb_128 = 1
+};
+
+enum atl1_dma_req_block {
+ atl1_dma_req_128 = 0,
+ atl1_dma_req_256 = 1,
+ atl1_dma_req_512 = 2,
+ atl1_dma_req_1024 = 3,
+ atl1_dma_req_2048 = 4,
+ atl1_dma_req_4096 = 5
+};
#define ATL1_MAX_INTR 3
#define ATL1_MAX_TX_BUF_LEN 0x3000 /* 12288 bytes */
@@ -58,19 +591,6 @@ struct atl1_adapter;
#define ATL1_RRD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_return_desc)
/*
- * This detached comment is preserved for documentation purposes only.
- * It was originally attached to some code that got deleted, but seems
- * important enough to keep around...
- *
- * <begin detached comment>
- * Some workarounds require millisecond delays and are run during interrupt
- * context. Most notably, when establishing link, the phy may need tweaking
- * but cannot process phy register reads/writes faster than millisecond
- * intervals...and we establish link due to a "link status change" interrupt.
- * <end detached comment>
- */
-
-/*
* atl1_ring_header represents a single, contiguous block of DMA space
* mapped for the three descriptor rings (tpd, rfd, rrd) and the two
* message blocks (cmb, smb) described below
@@ -156,20 +676,15 @@ struct atl1_sft_stats {
u64 tx_aborted_errors;
u64 tx_window_errors;
u64 tx_carrier_errors;
- u64 tx_pause; /* num pause packets transmitted. */
- u64 excecol; /* num tx packets w/ excessive collisions. */
- u64 deffer; /* num tx packets deferred */
- u64 scc; /* num packets subsequently transmitted
- * successfully w/ single prior collision. */
- u64 mcc; /* num packets subsequently transmitted
- * successfully w/ multiple prior collisions. */
- u64 latecol; /* num tx packets w/ late collisions. */
- u64 tx_underun; /* num tx packets aborted due to transmit
- * FIFO underrun, or TRD FIFO underrun */
- u64 tx_trunc; /* num tx packets truncated due to size
- * exceeding MTU, regardless whether truncated
- * by the chip or not. (The name doesn't really
- * reflect the meaning in this case.) */
+ u64 tx_pause; /* TX pause frames */
+ u64 excecol; /* TX packets w/ excessive collisions */
+ u64 deffer; /* TX packets deferred */
+ u64 scc; /* packets TX after a single collision */
+ u64 mcc; /* packets TX after multiple collisions */
+ u64 latecol; /* TX packets w/ late collisions */
+ u64 tx_underun; /* TX packets aborted due to TX FIFO underrun
+ * or TRD FIFO underrun */
+ u64 tx_trunc; /* TX packets truncated due to size > MTU */
u64 rx_pause; /* num Pause packets received. */
u64 rx_rrd_ov;
u64 rx_trunc;
@@ -184,8 +699,7 @@ struct atl1_hw {
enum atl1_dma_req_block dmar_block;
enum atl1_dma_req_block dmaw_block;
u8 preamble_len;
- u8 max_retry; /* Retransmission maximum, after which the
- * packet will be discarded */
+ u8 max_retry;
u8 jam_ipg; /* IPG to start JAM for collision based flow
* control in half-duplex mode. In units of
* 8-bit time */
@@ -271,16 +785,15 @@ struct atl1_adapter {
u64 hw_csum_err;
u64 hw_csum_good;
- u16 imt; /* interrupt moderator timer (2us resolution */
- u16 ict; /* interrupt clear timer (2us resolution */
- struct mii_if_info mii; /* MII interface info */
+ u16 imt; /* interrupt moderator timer (2us resolution) */
+ u16 ict; /* interrupt clear timer (2us resolution */
+ struct mii_if_info mii; /* MII interface info */
- /* structs defined in atl1_hw.h */
- u32 bd_number; /* board number */
+ u32 bd_number; /* board number */
bool pci_using_64;
struct atl1_hw hw;
struct atl1_smb smb;
struct atl1_cmb cmb;
};
-#endif /* _ATL1_H_ */
+#endif /* ATL1_H */
diff --git a/drivers/net/atlx/atl1_ethtool.c b/drivers/net/atlx/atl1_ethtool.c
deleted file mode 100644
index 68a83be..0000000
--- a/drivers/net/atlx/atl1_ethtool.c
+++ /dev/null
@@ -1,505 +0,0 @@
-/*
- * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
- * Copyright(c) 2006 Chris Snook <csnook@redhat.com>
- * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
- *
- * Derived from Intel e1000 driver
- * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59
- * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/ethtool.h>
-#include <linux/netdevice.h>
-#include <linux/mii.h>
-#include <asm/uaccess.h>
-
-#include "atl1.h"
-
-struct atl1_stats {
- char stat_string[ETH_GSTRING_LEN];
- int sizeof_stat;
- int stat_offset;
-};
-
-#define ATL1_STAT(m) sizeof(((struct atl1_adapter *)0)->m), \
- offsetof(struct atl1_adapter, m)
-
-static struct atl1_stats atl1_gstrings_stats[] = {
- {"rx_packets", ATL1_STAT(soft_stats.rx_packets)},
- {"tx_packets", ATL1_STAT(soft_stats.tx_packets)},
- {"rx_bytes", ATL1_STAT(soft_stats.rx_bytes)},
- {"tx_bytes", ATL1_STAT(soft_stats.tx_bytes)},
- {"rx_errors", ATL1_STAT(soft_stats.rx_errors)},
- {"tx_errors", ATL1_STAT(soft_stats.tx_errors)},
- {"rx_dropped", ATL1_STAT(net_stats.rx_dropped)},
- {"tx_dropped", ATL1_STAT(net_stats.tx_dropped)},
- {"multicast", ATL1_STAT(soft_stats.multicast)},
- {"collisions", ATL1_STAT(soft_stats.collisions)},
- {"rx_length_errors", ATL1_STAT(soft_stats.rx_length_errors)},
- {"rx_over_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
- {"rx_crc_errors", ATL1_STAT(soft_stats.rx_crc_errors)},
- {"rx_frame_errors", ATL1_STAT(soft_stats.rx_frame_errors)},
- {"rx_fifo_errors", ATL1_STAT(soft_stats.rx_fifo_errors)},
- {"rx_missed_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
- {"tx_aborted_errors", ATL1_STAT(soft_stats.tx_aborted_errors)},
- {"tx_carrier_errors", ATL1_STAT(soft_stats.tx_carrier_errors)},
- {"tx_fifo_errors", ATL1_STAT(soft_stats.tx_fifo_errors)},
- {"tx_window_errors", ATL1_STAT(soft_stats.tx_window_errors)},
- {"tx_abort_exce_coll", ATL1_STAT(soft_stats.excecol)},
- {"tx_abort_late_coll", ATL1_STAT(soft_stats.latecol)},
- {"tx_deferred_ok", ATL1_STAT(soft_stats.deffer)},
- {"tx_single_coll_ok", ATL1_STAT(soft_stats.scc)},
- {"tx_multi_coll_ok", ATL1_STAT(soft_stats.mcc)},
- {"tx_underun", ATL1_STAT(soft_stats.tx_underun)},
- {"tx_trunc", ATL1_STAT(soft_stats.tx_trunc)},
- {"tx_pause", ATL1_STAT(soft_stats.tx_pause)},
- {"rx_pause", ATL1_STAT(soft_stats.rx_pause)},
- {"rx_rrd_ov", ATL1_STAT(soft_stats.rx_rrd_ov)},
- {"rx_trunc", ATL1_STAT(soft_stats.rx_trunc)}
-};
-
-static void atl1_get_ethtool_stats(struct net_device *netdev,
- struct ethtool_stats *stats, u64 *data)
-{
- struct atl1_adapter *adapter = netdev_priv(netdev);
- int i;
- char *p;
-
- for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
- p = (char *)adapter+atl1_gstrings_stats[i].stat_offset;
- data[i] = (atl1_gstrings_stats[i].sizeof_stat ==
- sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
- }
-
-}
-
-static int atl1_get_sset_count(struct net_device *netdev, int sset)
-{
- switch (sset) {
- case ETH_SS_STATS:
- return ARRAY_SIZE(atl1_gstrings_stats);
- default:
- return -EOPNOTSUPP;
- }
-}
-
-static int atl1_get_settings(struct net_device *netdev,
- struct ethtool_cmd *ecmd)
-{
- struct atl1_adapter *adapter = netdev_priv(netdev);
- struct atl1_hw *hw = &adapter->hw;
-
- ecmd->supported = (SUPPORTED_10baseT_Half |
- SUPPORTED_10baseT_Full |
- SUPPORTED_100baseT_Half |
- SUPPORTED_100baseT_Full |
- SUPPORTED_1000baseT_Full |
- SUPPORTED_Autoneg | SUPPORTED_TP);
- ecmd->advertising = ADVERTISED_TP;
- if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
- hw->media_type == MEDIA_TYPE_1000M_FULL) {
- ecmd->advertising |= ADVERTISED_Autoneg;
- if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR) {
- ecmd->advertising |= ADVERTISED_Autoneg;
- ecmd->advertising |=
- (ADVERTISED_10baseT_Half |
- ADVERTISED_10baseT_Full |
- ADVERTISED_100baseT_Half |
- ADVERTISED_100baseT_Full |
- ADVERTISED_1000baseT_Full);
- }
- else
- ecmd->advertising |= (ADVERTISED_1000baseT_Full);
- }
- ecmd->port = PORT_TP;
- ecmd->phy_address = 0;
- ecmd->transceiver = XCVR_INTERNAL;
-
- if (netif_carrier_ok(adapter->netdev)) {
- u16 link_speed, link_duplex;
- atl1_get_speed_and_duplex(hw, &link_speed, &link_duplex);
- ecmd->speed = link_speed;
- if (link_duplex == FULL_DUPLEX)
- ecmd->duplex = DUPLEX_FULL;
- else
- ecmd->duplex = DUPLEX_HALF;
- } else {
- ecmd->speed = -1;
- ecmd->duplex = -1;
- }
- if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
- hw->media_type == MEDIA_TYPE_1000M_FULL)
- ecmd->autoneg = AUTONEG_ENABLE;
- else
- ecmd->autoneg = AUTONEG_DISABLE;
-
- return 0;
-}
-
-static int atl1_set_settings(struct net_device *netdev,
- struct ethtool_cmd *ecmd)
-{
- struct atl1_adapter *adapter = netdev_priv(netdev);
- struct atl1_hw *hw = &adapter->hw;
- u16 phy_data;
- int ret_val = 0;
- u16 old_media_type = hw->media_type;
-
- if (netif_running(adapter->netdev)) {
- dev_dbg(&adapter->pdev->dev, "ethtool shutting down adapter\n");
- atl1_down(adapter);
- }
-
- if (ecmd->autoneg == AUTONEG_ENABLE)
- hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
- else {
- if (ecmd->speed == SPEED_1000) {
- if (ecmd->duplex != DUPLEX_FULL) {
- dev_warn(&adapter->pdev->dev,
- "can't force to 1000M half duplex\n");
- ret_val = -EINVAL;
- goto exit_sset;
- }
- hw->media_type = MEDIA_TYPE_1000M_FULL;
- } else if (ecmd->speed == SPEED_100) {
- if (ecmd->duplex == DUPLEX_FULL) {
- hw->media_type = MEDIA_TYPE_100M_FULL;
- } else
- hw->media_type = MEDIA_TYPE_100M_HALF;
- } else {
- if (ecmd->duplex == DUPLEX_FULL)
- hw->media_type = MEDIA_TYPE_10M_FULL;
- else
- hw->media_type = MEDIA_TYPE_10M_HALF;
- }
- }
- switch (hw->media_type) {
- case MEDIA_TYPE_AUTO_SENSOR:
- ecmd->advertising =
- ADVERTISED_10baseT_Half |
- ADVERTISED_10baseT_Full |
- ADVERTISED_100baseT_Half |
- ADVERTISED_100baseT_Full |
- ADVERTISED_1000baseT_Full |
- ADVERTISED_Autoneg | ADVERTISED_TP;
- break;
- case MEDIA_TYPE_1000M_FULL:
- ecmd->advertising =
- ADVERTISED_1000baseT_Full |
- ADVERTISED_Autoneg | ADVERTISED_TP;
- break;
- default:
- ecmd->advertising = 0;
- break;
- }
- if (atl1_phy_setup_autoneg_adv(hw)) {
- ret_val = -EINVAL;
- dev_warn(&adapter->pdev->dev,
- "invalid ethtool speed/duplex setting\n");
- goto exit_sset;
- }
- if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
- hw->media_type == MEDIA_TYPE_1000M_FULL)
- phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
- else {
- switch (hw->media_type) {
- case MEDIA_TYPE_100M_FULL:
- phy_data =
- MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
- MII_CR_RESET;
- break;
- case MEDIA_TYPE_100M_HALF:
- phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
- break;
- case MEDIA_TYPE_10M_FULL:
- phy_data =
- MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
- break;
- default: /* MEDIA_TYPE_10M_HALF: */
- phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
- break;
- }
- }
- atl1_write_phy_reg(hw, MII_BMCR, phy_data);
-exit_sset:
- if (ret_val)
- hw->media_type = old_media_type;
-
- if (netif_running(adapter->netdev)) {
- dev_dbg(&adapter->pdev->dev, "ethtool starting adapter\n");
- atl1_up(adapter);
- } else if (!ret_val) {
- dev_dbg(&adapter->pdev->dev, "ethtool resetting adapter\n");
- atl1_reset(adapter);
- }
- return ret_val;
-}
-
-static void atl1_get_drvinfo(struct net_device *netdev,
- struct ethtool_drvinfo *drvinfo)
-{
- struct atl1_adapter *adapter = netdev_priv(netdev);
-
- strncpy(drvinfo->driver, atl1_driver_name, sizeof(drvinfo->driver));
- strncpy(drvinfo->version, atl1_driver_version,
- sizeof(drvinfo->version));
- strncpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
- strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
- sizeof(drvinfo->bus_info));
- drvinfo->eedump_len = ATL1_EEDUMP_LEN;
-}
-
-static void atl1_get_wol(struct net_device *netdev,
- struct ethtool_wolinfo *wol)
-{
- struct atl1_adapter *adapter = netdev_priv(netdev);
-
- wol->supported = WAKE_UCAST | WAKE_MCAST | WAKE_BCAST | WAKE_MAGIC;
- wol->wolopts = 0;
- if (adapter->wol & ATL1_WUFC_EX)
- wol->wolopts |= WAKE_UCAST;
- if (adapter->wol & ATL1_WUFC_MC)
- wol->wolopts |= WAKE_MCAST;
- if (adapter->wol & ATL1_WUFC_BC)
- wol->wolopts |= WAKE_BCAST;
- if (adapter->wol & ATL1_WUFC_MAG)
- wol->wolopts |= WAKE_MAGIC;
- return;
-}
-
-static int atl1_set_wol(struct net_device *netdev,
- struct ethtool_wolinfo *wol)
-{
- struct atl1_adapter *adapter = netdev_priv(netdev);
-
- if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
- return -EOPNOTSUPP;
- adapter->wol = 0;
- if (wol->wolopts & WAKE_UCAST)
- adapter->wol |= ATL1_WUFC_EX;
- if (wol->wolopts & WAKE_MCAST)
- adapter->wol |= ATL1_WUFC_MC;
- if (wol->wolopts & WAKE_BCAST)
- adapter->wol |= ATL1_WUFC_BC;
- if (wol->wolopts & WAKE_MAGIC)
- adapter->wol |= ATL1_WUFC_MAG;
- return 0;
-}
-
-static void atl1_get_ringparam(struct net_device *netdev,
- struct ethtool_ringparam *ring)
-{
- struct atl1_adapter *adapter = netdev_priv(netdev);
- struct atl1_tpd_ring *txdr = &adapter->tpd_ring;
- struct atl1_rfd_ring *rxdr = &adapter->rfd_ring;
-
- ring->rx_max_pending = ATL1_MAX_RFD;
- ring->tx_max_pending = ATL1_MAX_TPD;
- ring->rx_mini_max_pending = 0;
- ring->rx_jumbo_max_pending = 0;
- ring->rx_pending = rxdr->count;
- ring->tx_pending = txdr->count;
- ring->rx_mini_pending = 0;
- ring->rx_jumbo_pending = 0;
-}
-
-static int atl1_set_ringparam(struct net_device *netdev,
- struct ethtool_ringparam *ring)
-{
- struct atl1_adapter *adapter = netdev_priv(netdev);
- struct atl1_tpd_ring *tpdr = &adapter->tpd_ring;
- struct atl1_rrd_ring *rrdr = &adapter->rrd_ring;
- struct atl1_rfd_ring *rfdr = &adapter->rfd_ring;
-
- struct atl1_tpd_ring tpd_old, tpd_new;
- struct atl1_rfd_ring rfd_old, rfd_new;
- struct atl1_rrd_ring rrd_old, rrd_new;
- struct atl1_ring_header rhdr_old, rhdr_new;
- int err;
-
- tpd_old = adapter->tpd_ring;
- rfd_old = adapter->rfd_ring;
- rrd_old = adapter->rrd_ring;
- rhdr_old = adapter->ring_header;
-
- if (netif_running(adapter->netdev))
- atl1_down(adapter);
-
- rfdr->count = (u16) max(ring->rx_pending, (u32) ATL1_MIN_RFD);
- rfdr->count = rfdr->count > ATL1_MAX_RFD ? ATL1_MAX_RFD :
- rfdr->count;
- rfdr->count = (rfdr->count + 3) & ~3;
- rrdr->count = rfdr->count;
-
- tpdr->count = (u16) max(ring->tx_pending, (u32) ATL1_MIN_TPD);
- tpdr->count = tpdr->count > ATL1_MAX_TPD ? ATL1_MAX_TPD :
- tpdr->count;
- tpdr->count = (tpdr->count + 3) & ~3;
-
- if (netif_running(adapter->netdev)) {
- /* try to get new resources before deleting old */
- err = atl1_setup_ring_resources(adapter);
- if (err)
- goto err_setup_ring;
-
- /*
- * save the new, restore the old in order to free it,
- * then restore the new back again
- */
-
- rfd_new = adapter->rfd_ring;
- rrd_new = adapter->rrd_ring;
- tpd_new = adapter->tpd_ring;
- rhdr_new = adapter->ring_header;
- adapter->rfd_ring = rfd_old;
- adapter->rrd_ring = rrd_old;
- adapter->tpd_ring = tpd_old;
- adapter->ring_header = rhdr_old;
- atl1_free_ring_resources(adapter);
- adapter->rfd_ring = rfd_new;
- adapter->rrd_ring = rrd_new;
- adapter->tpd_ring = tpd_new;
- adapter->ring_header = rhdr_new;
-
- err = atl1_up(adapter);
- if (err)
- return err;
- }
- return 0;
-
-err_setup_ring:
- adapter->rfd_ring = rfd_old;
- adapter->rrd_ring = rrd_old;
- adapter->tpd_ring = tpd_old;
- adapter->ring_header = rhdr_old;
- atl1_up(adapter);
- return err;
-}
-
-static void atl1_get_pauseparam(struct net_device *netdev,
- struct ethtool_pauseparam *epause)
-{
- struct atl1_adapter *adapter = netdev_priv(netdev);
- struct atl1_hw *hw = &adapter->hw;
-
- if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
- hw->media_type == MEDIA_TYPE_1000M_FULL) {
- epause->autoneg = AUTONEG_ENABLE;
- } else {
- epause->autoneg = AUTONEG_DISABLE;
- }
- epause->rx_pause = 1;
- epause->tx_pause = 1;
-}
-
-static int atl1_set_pauseparam(struct net_device *netdev,
- struct ethtool_pauseparam *epause)
-{
- struct atl1_adapter *adapter = netdev_priv(netdev);
- struct atl1_hw *hw = &adapter->hw;
-
- if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
- hw->media_type == MEDIA_TYPE_1000M_FULL) {
- epause->autoneg = AUTONEG_ENABLE;
- } else {
- epause->autoneg = AUTONEG_DISABLE;
- }
-
- epause->rx_pause = 1;
- epause->tx_pause = 1;
-
- return 0;
-}
-
-static u32 atl1_get_rx_csum(struct net_device *netdev)
-{
- return 1;
-}
-
-static void atl1_get_strings(struct net_device *netdev, u32 stringset,
- u8 *data)
-{
- u8 *p = data;
- int i;
-
- switch (stringset) {
- case ETH_SS_STATS:
- for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
- memcpy(p, atl1_gstrings_stats[i].stat_string,
- ETH_GSTRING_LEN);
- p += ETH_GSTRING_LEN;
- }
- break;
- }
-}
-
-static int atl1_nway_reset(struct net_device *netdev)
-{
- struct atl1_adapter *adapter = netdev_priv(netdev);
- struct atl1_hw *hw = &adapter->hw;
-
- if (netif_running(netdev)) {
- u16 phy_data;
- atl1_down(adapter);
-
- if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
- hw->media_type == MEDIA_TYPE_1000M_FULL) {
- phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
- } else {
- switch (hw->media_type) {
- case MEDIA_TYPE_100M_FULL:
- phy_data = MII_CR_FULL_DUPLEX |
- MII_CR_SPEED_100 | MII_CR_RESET;
- break;
- case MEDIA_TYPE_100M_HALF:
- phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
- break;
- case MEDIA_TYPE_10M_FULL:
- phy_data = MII_CR_FULL_DUPLEX |
- MII_CR_SPEED_10 | MII_CR_RESET;
- break;
- default: /* MEDIA_TYPE_10M_HALF */
- phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
- }
- }
- atl1_write_phy_reg(hw, MII_BMCR, phy_data);
- atl1_up(adapter);
- }
- return 0;
-}
-
-const struct ethtool_ops atl1_ethtool_ops = {
- .get_settings = atl1_get_settings,
- .set_settings = atl1_set_settings,
- .get_drvinfo = atl1_get_drvinfo,
- .get_wol = atl1_get_wol,
- .set_wol = atl1_set_wol,
- .get_ringparam = atl1_get_ringparam,
- .set_ringparam = atl1_set_ringparam,
- .get_pauseparam = atl1_get_pauseparam,
- .set_pauseparam = atl1_set_pauseparam,
- .get_rx_csum = atl1_get_rx_csum,
- .set_tx_csum = ethtool_op_set_tx_hw_csum,
- .get_link = ethtool_op_get_link,
- .set_sg = ethtool_op_set_sg,
- .get_strings = atl1_get_strings,
- .nway_reset = atl1_nway_reset,
- .get_ethtool_stats = atl1_get_ethtool_stats,
- .get_sset_count = atl1_get_sset_count,
- .set_tso = ethtool_op_set_tso,
-};
diff --git a/drivers/net/atlx/atl1_hw.c b/drivers/net/atlx/atl1_hw.c
deleted file mode 100644
index 9d3bd22..0000000
--- a/drivers/net/atlx/atl1_hw.c
+++ /dev/null
@@ -1,720 +0,0 @@
-/*
- * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
- * Copyright(c) 2006 Chris Snook <csnook@redhat.com>
- * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
- *
- * Derived from Intel e1000 driver
- * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59
- * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/delay.h>
-#include <linux/if_vlan.h>
-#include <linux/etherdevice.h>
-#include <linux/crc32.h>
-#include <asm/byteorder.h>
-
-#include "atl1.h"
-
-/*
- * Reset the transmit and receive units; mask and clear all interrupts.
- * hw - Struct containing variables accessed by shared code
- * return : ATL1_SUCCESS or idle status (if error)
- */
-s32 atl1_reset_hw(struct atl1_hw *hw)
-{
- struct pci_dev *pdev = hw->back->pdev;
- u32 icr;
- int i;
-
- /*
- * Clear Interrupt mask to stop board from generating
- * interrupts & Clear any pending interrupt events
- */
- /*
- * iowrite32(0, hw->hw_addr + REG_IMR);
- * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
- */
-
- /*
- * Issue Soft Reset to the MAC. This will reset the chip's
- * transmit, receive, DMA. It will not effect
- * the current PCI configuration. The global reset bit is self-
- * clearing, and should clear within a microsecond.
- */
- iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
- ioread32(hw->hw_addr + REG_MASTER_CTRL);
-
- iowrite16(1, hw->hw_addr + REG_GPHY_ENABLE);
- ioread16(hw->hw_addr + REG_GPHY_ENABLE);
-
- msleep(1); /* delay about 1ms */
-
- /* Wait at least 10ms for All module to be Idle */
- for (i = 0; i < 10; i++) {
- icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
- if (!icr)
- break;
- msleep(1); /* delay 1 ms */
- cpu_relax(); /* FIXME: is this still the right way to do this? */
- }
-
- if (icr) {
- dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr);
- return icr;
- }
-
- return ATL1_SUCCESS;
-}
-
-/* function about EEPROM
- *
- * check_eeprom_exist
- * return 0 if eeprom exist
- */
-static int atl1_check_eeprom_exist(struct atl1_hw *hw)
-{
- u32 value;
- value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
- if (value & SPI_FLASH_CTRL_EN_VPD) {
- value &= ~SPI_FLASH_CTRL_EN_VPD;
- iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
- }
-
- value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
- return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
-}
-
-static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
-{
- int i;
- u32 control;
-
- if (offset & 3)
- return false; /* address do not align */
-
- iowrite32(0, hw->hw_addr + REG_VPD_DATA);
- control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
- iowrite32(control, hw->hw_addr + REG_VPD_CAP);
- ioread32(hw->hw_addr + REG_VPD_CAP);
-
- for (i = 0; i < 10; i++) {
- msleep(2);
- control = ioread32(hw->hw_addr + REG_VPD_CAP);
- if (control & VPD_CAP_VPD_FLAG)
- break;
- }
- if (control & VPD_CAP_VPD_FLAG) {
- *p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
- return true;
- }
- return false; /* timeout */
-}
-
-/*
- * Reads the value from a PHY register
- * hw - Struct containing variables accessed by shared code
- * reg_addr - address of the PHY register to read
- */
-s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
-{
- u32 val;
- int i;
-
- val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
- MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
- MDIO_CLK_SEL_SHIFT;
- iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
- ioread32(hw->hw_addr + REG_MDIO_CTRL);
-
- for (i = 0; i < MDIO_WAIT_TIMES; i++) {
- udelay(2);
- val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
- if (!(val & (MDIO_START | MDIO_BUSY)))
- break;
- }
- if (!(val & (MDIO_START | MDIO_BUSY))) {
- *phy_data = (u16) val;
- return ATL1_SUCCESS;
- }
- return ATL1_ERR_PHY;
-}
-
-#define CUSTOM_SPI_CS_SETUP 2
-#define CUSTOM_SPI_CLK_HI 2
-#define CUSTOM_SPI_CLK_LO 2
-#define CUSTOM_SPI_CS_HOLD 2
-#define CUSTOM_SPI_CS_HI 3
-
-static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
-{
- int i;
- u32 value;
-
- iowrite32(0, hw->hw_addr + REG_SPI_DATA);
- iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
-
- value = SPI_FLASH_CTRL_WAIT_READY |
- (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
- SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
- SPI_FLASH_CTRL_CLK_HI_MASK) <<
- SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
- SPI_FLASH_CTRL_CLK_LO_MASK) <<
- SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
- SPI_FLASH_CTRL_CS_HOLD_MASK) <<
- SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
- SPI_FLASH_CTRL_CS_HI_MASK) <<
- SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
- SPI_FLASH_CTRL_INS_SHIFT;
-
- iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
-
- value |= SPI_FLASH_CTRL_START;
- iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
- ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
-
- for (i = 0; i < 10; i++) {
- msleep(1); /* 1ms */
- value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
- if (!(value & SPI_FLASH_CTRL_START))
- break;
- }
-
- if (value & SPI_FLASH_CTRL_START)
- return false;
-
- *buf = ioread32(hw->hw_addr + REG_SPI_DATA);
-
- return true;
-}
-
-/*
- * get_permanent_address
- * return 0 if get valid mac address,
- */
-static int atl1_get_permanent_address(struct atl1_hw *hw)
-{
- u32 addr[2];
- u32 i, control;
- u16 reg;
- u8 eth_addr[ETH_ALEN];
- bool key_valid;
-
- if (is_valid_ether_addr(hw->perm_mac_addr))
- return 0;
-
- /* init */
- addr[0] = addr[1] = 0;
-
- if (!atl1_check_eeprom_exist(hw)) { /* eeprom exist */
- reg = 0;
- key_valid = false;
- /* Read out all EEPROM content */
- i = 0;
- while (1) {
- if (atl1_read_eeprom(hw, i + 0x100, &control)) {
- if (key_valid) {
- if (reg == REG_MAC_STA_ADDR)
- addr[0] = control;
- else if (reg == (REG_MAC_STA_ADDR + 4))
- addr[1] = control;
- key_valid = false;
- } else if ((control & 0xff) == 0x5A) {
- key_valid = true;
- reg = (u16) (control >> 16);
- } else
- break; /* assume data end while encount an invalid KEYWORD */
- } else
- break; /* read error */
- i += 4;
- }
-
- *(u32 *) ð_addr[2] = swab32(addr[0]);
- *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]);
- if (is_valid_ether_addr(eth_addr)) {
- memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
- return 0;
- }
- return 1;
- }
-
- /* see if SPI FLAGS exist ? */
- addr[0] = addr[1] = 0;
- reg = 0;
- key_valid = false;
- i = 0;
- while (1) {
- if (atl1_spi_read(hw, i + 0x1f000, &control)) {
- if (key_valid) {
- if (reg == REG_MAC_STA_ADDR)
- addr[0] = control;
- else if (reg == (REG_MAC_STA_ADDR + 4))
- addr[1] = control;
- key_valid = false;
- } else if ((control & 0xff) == 0x5A) {
- key_valid = true;
- reg = (u16) (control >> 16);
- } else
- break; /* data end */
- } else
- break; /* read error */
- i += 4;
- }
-
- *(u32 *) ð_addr[2] = swab32(addr[0]);
- *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]);
- if (is_valid_ether_addr(eth_addr)) {
- memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
- return 0;
- }
-
- /*
- * On some motherboards, the MAC address is written by the
- * BIOS directly to the MAC register during POST, and is
- * not stored in eeprom. If all else thus far has failed
- * to fetch the permanent MAC address, try reading it directly.
- */
- addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
- addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
- *(u32 *) ð_addr[2] = swab32(addr[0]);
- *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]);
- if (is_valid_ether_addr(eth_addr)) {
- memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
- return 0;
- }
-
- return 1;
-}
-
-/*
- * Reads the adapter's MAC address from the EEPROM
- * hw - Struct containing variables accessed by shared code
- */
-s32 atl1_read_mac_addr(struct atl1_hw *hw)
-{
- u16 i;
-
- if (atl1_get_permanent_address(hw))
- random_ether_addr(hw->perm_mac_addr);
-
- for (i = 0; i < ETH_ALEN; i++)
- hw->mac_addr[i] = hw->perm_mac_addr[i];
- return ATL1_SUCCESS;
-}
-
-/*
- * Hashes an address to determine its location in the multicast table
- * hw - Struct containing variables accessed by shared code
- * mc_addr - the multicast address to hash
- *
- * atl1_hash_mc_addr
- * purpose
- * set hash value for a multicast address
- * hash calcu processing :
- * 1. calcu 32bit CRC for multicast address
- * 2. reverse crc with MSB to LSB
- */
-u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
-{
- u32 crc32, value = 0;
- int i;
-
- crc32 = ether_crc_le(6, mc_addr);
- for (i = 0; i < 32; i++)
- value |= (((crc32 >> i) & 1) << (31 - i));
-
- return value;
-}
-
-/*
- * Sets the bit in the multicast table corresponding to the hash value.
- * hw - Struct containing variables accessed by shared code
- * hash_value - Multicast address hash value
- */
-void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
-{
- u32 hash_bit, hash_reg;
- u32 mta;
-
- /*
- * The HASH Table is a register array of 2 32-bit registers.
- * It is treated like an array of 64 bits. We want to set
- * bit BitArray[hash_value]. So we figure out what register
- * the bit is in, read it, OR in the new bit, then write
- * back the new value. The register is determined by the
- * upper 7 bits of the hash value and the bit within that
- * register are determined by the lower 5 bits of the value.
- */
- hash_reg = (hash_value >> 31) & 0x1;
- hash_bit = (hash_value >> 26) & 0x1F;
- mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
- mta |= (1 << hash_bit);
- iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
-}
-
-/*
- * Writes a value to a PHY register
- * hw - Struct containing variables accessed by shared code
- * reg_addr - address of the PHY register to write
- * data - data to write to the PHY
- */
-s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
-{
- int i;
- u32 val;
-
- val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
- (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
- MDIO_SUP_PREAMBLE |
- MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
- iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
- ioread32(hw->hw_addr + REG_MDIO_CTRL);
-
- for (i = 0; i < MDIO_WAIT_TIMES; i++) {
- udelay(2);
- val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
- if (!(val & (MDIO_START | MDIO_BUSY)))
- break;
- }
-
- if (!(val & (MDIO_START | MDIO_BUSY)))
- return ATL1_SUCCESS;
-
- return ATL1_ERR_PHY;
-}
-
-/*
- * Make L001's PHY out of Power Saving State (bug)
- * hw - Struct containing variables accessed by shared code
- * when power on, L001's PHY always on Power saving State
- * (Gigabit Link forbidden)
- */
-static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
-{
- s32 ret;
- ret = atl1_write_phy_reg(hw, 29, 0x0029);
- if (ret)
- return ret;
- return atl1_write_phy_reg(hw, 30, 0);
-}
-
-/*
- *TODO: do something or get rid of this
- */
-s32 atl1_phy_enter_power_saving(struct atl1_hw *hw)
-{
-/* s32 ret_val;
- * u16 phy_data;
- */
-
-/*
- ret_val = atl1_write_phy_reg(hw, ...);
- ret_val = atl1_write_phy_reg(hw, ...);
- ....
-*/
- return ATL1_SUCCESS;
-}
-
-/*
- * Resets the PHY and make all config validate
- * hw - Struct containing variables accessed by shared code
- *
- * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
- */
-static s32 atl1_phy_reset(struct atl1_hw *hw)
-{
- struct pci_dev *pdev = hw->back->pdev;
- s32 ret_val;
- u16 phy_data;
-
- if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
- hw->media_type == MEDIA_TYPE_1000M_FULL)
- phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
- else {
- switch (hw->media_type) {
- case MEDIA_TYPE_100M_FULL:
- phy_data =
- MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
- MII_CR_RESET;
- break;
- case MEDIA_TYPE_100M_HALF:
- phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
- break;
- case MEDIA_TYPE_10M_FULL:
- phy_data =
- MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
- break;
- default: /* MEDIA_TYPE_10M_HALF: */
- phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
- break;
- }
- }
-
- ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
- if (ret_val) {
- u32 val;
- int i;
- /* pcie serdes link may be down! */
- dev_dbg(&pdev->dev, "pcie phy link down\n");
-
- for (i = 0; i < 25; i++) {
- msleep(1);
- val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
- if (!(val & (MDIO_START | MDIO_BUSY)))
- break;
- }
-
- if ((val & (MDIO_START | MDIO_BUSY)) != 0) {
- dev_warn(&pdev->dev, "pcie link down at least 25ms\n");
- return ret_val;
- }
- }
- return ATL1_SUCCESS;
-}
-
-/*
- * Configures PHY autoneg and flow control advertisement settings
- * hw - Struct containing variables accessed by shared code
- */
-s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
-{
- s32 ret_val;
- s16 mii_autoneg_adv_reg;
- s16 mii_1000t_ctrl_reg;
-
- /* Read the MII Auto-Neg Advertisement Register (Address 4). */
- mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
-
- /* Read the MII 1000Base-T Control Register (Address 9). */
- mii_1000t_ctrl_reg = MII_AT001_CR_1000T_DEFAULT_CAP_MASK;
-
- /*
- * First we clear all the 10/100 mb speed bits in the Auto-Neg
- * Advertisement Register (Address 4) and the 1000 mb speed bits in
- * the 1000Base-T Control Register (Address 9).
- */
- mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
- mii_1000t_ctrl_reg &= ~MII_AT001_CR_1000T_SPEED_MASK;
-
- /*
- * Need to parse media_type and set up
- * the appropriate PHY registers.
- */
- switch (hw->media_type) {
- case MEDIA_TYPE_AUTO_SENSOR:
- mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
- MII_AR_10T_FD_CAPS |
- MII_AR_100TX_HD_CAPS |
- MII_AR_100TX_FD_CAPS);
- mii_1000t_ctrl_reg |= MII_AT001_CR_1000T_FD_CAPS;
- break;
-
- case MEDIA_TYPE_1000M_FULL:
- mii_1000t_ctrl_reg |= MII_AT001_CR_1000T_FD_CAPS;
- break;
-
- case MEDIA_TYPE_100M_FULL:
- mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
- break;
-
- case MEDIA_TYPE_100M_HALF:
- mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
- break;
-
- case MEDIA_TYPE_10M_FULL:
- mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
- break;
-
- default:
- mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
- break;
- }
-
- /* flow control fixed to enable all */
- mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
-
- hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
- hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
-
- ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
- if (ret_val)
- return ret_val;
-
- ret_val = atl1_write_phy_reg(hw, MII_AT001_CR, mii_1000t_ctrl_reg);
- if (ret_val)
- return ret_val;
-
- return ATL1_SUCCESS;
-}
-
-/*
- * Configures link settings.
- * hw - Struct containing variables accessed by shared code
- * Assumes the hardware has previously been reset and the
- * transmitter and receiver are not enabled.
- */
-static s32 atl1_setup_link(struct atl1_hw *hw)
-{
- struct pci_dev *pdev = hw->back->pdev;
- s32 ret_val;
-
- /*
- * Options:
- * PHY will advertise value(s) parsed from
- * autoneg_advertised and fc
- * no matter what autoneg is , We will not wait link result.
- */
- ret_val = atl1_phy_setup_autoneg_adv(hw);
- if (ret_val) {
- dev_dbg(&pdev->dev, "error setting up autonegotiation\n");
- return ret_val;
- }
- /* SW.Reset , En-Auto-Neg if needed */
- ret_val = atl1_phy_reset(hw);
- if (ret_val) {
- dev_dbg(&pdev->dev, "error resetting phy\n");
- return ret_val;
- }
- hw->phy_configured = true;
- return ret_val;
-}
-
-static struct atl1_spi_flash_dev flash_table[] = {
-/* MFR_NAME WRSR READ PRGM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */
- {"Atmel", 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62},
- {"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60},
- {"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7},
-};
-
-static void atl1_init_flash_opcode(struct atl1_hw *hw)
-{
- if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
- hw->flash_vendor = 0; /* ATMEL */
-
- /* Init OP table */
- iowrite8(flash_table[hw->flash_vendor].cmd_program,
- hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
- iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
- hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
- iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
- hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
- iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
- hw->hw_addr + REG_SPI_FLASH_OP_RDID);
- iowrite8(flash_table[hw->flash_vendor].cmd_wren,
- hw->hw_addr + REG_SPI_FLASH_OP_WREN);
- iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
- hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
- iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
- hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
- iowrite8(flash_table[hw->flash_vendor].cmd_read,
- hw->hw_addr + REG_SPI_FLASH_OP_READ);
-}
-
-/*
- * Performs basic configuration of the adapter.
- * hw - Struct containing variables accessed by shared code
- * Assumes that the controller has previously been reset and is in a
- * post-reset uninitialized state. Initializes multicast table,
- * and Calls routines to setup link
- * Leaves the transmit and receive units disabled and uninitialized.
- */
-s32 atl1_init_hw(struct atl1_hw *hw)
-{
- u32 ret_val = 0;
-
- /* Zero out the Multicast HASH table */
- iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
- /* clear the old settings from the multicast hash table */
- iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
-
- atl1_init_flash_opcode(hw);
-
- if (!hw->phy_configured) {
- /* enable GPHY LinkChange Interrrupt */
- ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
- if (ret_val)
- return ret_val;
- /* make PHY out of power-saving state */
- ret_val = atl1_phy_leave_power_saving(hw);
- if (ret_val)
- return ret_val;
- /* Call a subroutine to configure the link */
- ret_val = atl1_setup_link(hw);
- }
- return ret_val;
-}
-
-/*
- * Detects the current speed and duplex settings of the hardware.
- * hw - Struct containing variables accessed by shared code
- * speed - Speed of the connection
- * duplex - Duplex setting of the connection
- */
-s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
-{
- struct pci_dev *pdev = hw->back->pdev;
- s32 ret_val;
- u16 phy_data;
-
- /* ; --- Read PHY Specific Status Register (17) */
- ret_val = atl1_read_phy_reg(hw, MII_AT001_PSSR, &phy_data);
- if (ret_val)
- return ret_val;
-
- if (!(phy_data & MII_AT001_PSSR_SPD_DPLX_RESOLVED))
- return ATL1_ERR_PHY_RES;
-
- switch (phy_data & MII_AT001_PSSR_SPEED) {
- case MII_AT001_PSSR_1000MBS:
- *speed = SPEED_1000;
- break;
- case MII_AT001_PSSR_100MBS:
- *speed = SPEED_100;
- break;
- case MII_AT001_PSSR_10MBS:
- *speed = SPEED_10;
- break;
- default:
- dev_dbg(&pdev->dev, "error getting speed\n");
- return ATL1_ERR_PHY_SPEED;
- break;
- }
- if (phy_data & MII_AT001_PSSR_DPLX)
- *duplex = FULL_DUPLEX;
- else
- *duplex = HALF_DUPLEX;
-
- return ATL1_SUCCESS;
-}
-
-void atl1_set_mac_addr(struct atl1_hw *hw)
-{
- u32 value;
- /*
- * 00-0B-6A-F6-00-DC
- * 0: 6AF600DC 1: 000B
- * low dword
- */
- value = (((u32) hw->mac_addr[2]) << 24) |
- (((u32) hw->mac_addr[3]) << 16) |
- (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
- iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
- /* high dword */
- value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
- iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
-}
diff --git a/drivers/net/atlx/atl1_hw.h b/drivers/net/atlx/atl1_hw.h
deleted file mode 100644
index 939aa0f..0000000
--- a/drivers/net/atlx/atl1_hw.h
+++ /dev/null
@@ -1,946 +0,0 @@
-/*
- * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
- * Copyright(c) 2006 Chris Snook <csnook@redhat.com>
- * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
- *
- * Derived from Intel e1000 driver
- * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59
- * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * There are a lot of defines in here that are unused and/or have cryptic
- * names. Please leave them alone, as they're the closest thing we have
- * to a spec from Attansic at present. *ahem* -- CHS
- */
-
-#ifndef _ATL1_HW_H_
-#define _ATL1_HW_H_
-
-#include <linux/types.h>
-#include <linux/mii.h>
-
-struct atl1_adapter;
-struct atl1_hw;
-
-/* function prototypes needed by multiple files */
-s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw);
-s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data);
-s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex);
-s32 atl1_read_mac_addr(struct atl1_hw *hw);
-s32 atl1_init_hw(struct atl1_hw *hw);
-s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex);
-s32 atl1_set_speed_and_duplex(struct atl1_hw *hw, u16 speed, u16 duplex);
-u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr);
-void atl1_hash_set(struct atl1_hw *hw, u32 hash_value);
-s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data);
-void atl1_set_mac_addr(struct atl1_hw *hw);
-s32 atl1_phy_enter_power_saving(struct atl1_hw *hw);
-s32 atl1_reset_hw(struct atl1_hw *hw);
-void atl1_check_options(struct atl1_adapter *adapter);
-
-/* register definitions */
-#define REG_PCIE_CAP_LIST 0x58
-
-#define REG_VPD_CAP 0x6C
-#define VPD_CAP_ID_MASK 0xff
-#define VPD_CAP_ID_SHIFT 0
-#define VPD_CAP_NEXT_PTR_MASK 0xFF
-#define VPD_CAP_NEXT_PTR_SHIFT 8
-#define VPD_CAP_VPD_ADDR_MASK 0x7FFF
-#define VPD_CAP_VPD_ADDR_SHIFT 16
-#define VPD_CAP_VPD_FLAG 0x80000000
-
-#define REG_VPD_DATA 0x70
-
-#define REG_SPI_FLASH_CTRL 0x200
-#define SPI_FLASH_CTRL_STS_NON_RDY 0x1
-#define SPI_FLASH_CTRL_STS_WEN 0x2
-#define SPI_FLASH_CTRL_STS_WPEN 0x80
-#define SPI_FLASH_CTRL_DEV_STS_MASK 0xFF
-#define SPI_FLASH_CTRL_DEV_STS_SHIFT 0
-#define SPI_FLASH_CTRL_INS_MASK 0x7
-#define SPI_FLASH_CTRL_INS_SHIFT 8
-#define SPI_FLASH_CTRL_START 0x800
-#define SPI_FLASH_CTRL_EN_VPD 0x2000
-#define SPI_FLASH_CTRL_LDSTART 0x8000
-#define SPI_FLASH_CTRL_CS_HI_MASK 0x3
-#define SPI_FLASH_CTRL_CS_HI_SHIFT 16
-#define SPI_FLASH_CTRL_CS_HOLD_MASK 0x3
-#define SPI_FLASH_CTRL_CS_HOLD_SHIFT 18
-#define SPI_FLASH_CTRL_CLK_LO_MASK 0x3
-#define SPI_FLASH_CTRL_CLK_LO_SHIFT 20
-#define SPI_FLASH_CTRL_CLK_HI_MASK 0x3
-#define SPI_FLASH_CTRL_CLK_HI_SHIFT 22
-#define SPI_FLASH_CTRL_CS_SETUP_MASK 0x3
-#define SPI_FLASH_CTRL_CS_SETUP_SHIFT 24
-#define SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3
-#define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26
-#define SPI_FLASH_CTRL_WAIT_READY 0x10000000
-
-#define REG_SPI_ADDR 0x204
-
-#define REG_SPI_DATA 0x208
-
-#define REG_SPI_FLASH_CONFIG 0x20C
-#define SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF
-#define SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0
-#define SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3
-#define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24
-#define SPI_FLASH_CONFIG_LD_EXIST 0x4000000
-
-#define REG_SPI_FLASH_OP_PROGRAM 0x210
-#define REG_SPI_FLASH_OP_SC_ERASE 0x211
-#define REG_SPI_FLASH_OP_CHIP_ERASE 0x212
-#define REG_SPI_FLASH_OP_RDID 0x213
-#define REG_SPI_FLASH_OP_WREN 0x214
-#define REG_SPI_FLASH_OP_RDSR 0x215
-#define REG_SPI_FLASH_OP_WRSR 0x216
-#define REG_SPI_FLASH_OP_READ 0x217
-
-#define REG_TWSI_CTRL 0x218
-#define TWSI_CTRL_LD_OFFSET_MASK 0xFF
-#define TWSI_CTRL_LD_OFFSET_SHIFT 0
-#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7
-#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8
-#define TWSI_CTRL_SW_LDSTART 0x800
-#define TWSI_CTRL_HW_LDSTART 0x1000
-#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x7F
-#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15
-#define TWSI_CTRL_LD_EXIST 0x400000
-#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3
-#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23
-#define TWSI_CTRL_FREQ_SEL_100K 0
-#define TWSI_CTRL_FREQ_SEL_200K 1
-#define TWSI_CTRL_FREQ_SEL_300K 2
-#define TWSI_CTRL_FREQ_SEL_400K 3
-#define TWSI_CTRL_SMB_SLV_ADDR
-#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3
-#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24
-
-#define REG_PCIE_DEV_MISC_CTRL 0x21C
-#define PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2
-#define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1
-#define PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4
-#define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8
-#define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10
-
-/* Selene Master Control Register */
-#define REG_MASTER_CTRL 0x1400
-#define MASTER_CTRL_SOFT_RST 0x1
-#define MASTER_CTRL_MTIMER_EN 0x2
-#define MASTER_CTRL_ITIMER_EN 0x4
-#define MASTER_CTRL_MANUAL_INT 0x8
-#define MASTER_CTRL_REV_NUM_SHIFT 16
-#define MASTER_CTRL_REV_NUM_MASK 0xff
-#define MASTER_CTRL_DEV_ID_SHIFT 24
-#define MASTER_CTRL_DEV_ID_MASK 0xff
-
-/* Timer Initial Value Register */
-#define REG_MANUAL_TIMER_INIT 0x1404
-
-/* IRQ ModeratorTimer Initial Value Register */
-#define REG_IRQ_MODU_TIMER_INIT 0x1408
-
-#define REG_GPHY_ENABLE 0x140C
-
-/* IRQ Anti-Lost Timer Initial Value Register */
-#define REG_CMBDISDMA_TIMER 0x140E
-
-/* Block IDLE Status Register */
-#define REG_IDLE_STATUS 0x1410
-#define IDLE_STATUS_RXMAC 1
-#define IDLE_STATUS_TXMAC 2
-#define IDLE_STATUS_RXQ 4
-#define IDLE_STATUS_TXQ 8
-#define IDLE_STATUS_DMAR 0x10
-#define IDLE_STATUS_DMAW 0x20
-#define IDLE_STATUS_SMB 0x40
-#define IDLE_STATUS_CMB 0x80
-
-/* MDIO Control Register */
-#define REG_MDIO_CTRL 0x1414
-#define MDIO_DATA_MASK 0xffff
-#define MDIO_DATA_SHIFT 0
-#define MDIO_REG_ADDR_MASK 0x1f
-#define MDIO_REG_ADDR_SHIFT 16
-#define MDIO_RW 0x200000
-#define MDIO_SUP_PREAMBLE 0x400000
-#define MDIO_START 0x800000
-#define MDIO_CLK_SEL_SHIFT 24
-#define MDIO_CLK_25_4 0
-#define MDIO_CLK_25_6 2
-#define MDIO_CLK_25_8 3
-#define MDIO_CLK_25_10 4
-#define MDIO_CLK_25_14 5
-#define MDIO_CLK_25_20 6
-#define MDIO_CLK_25_28 7
-#define MDIO_BUSY 0x8000000
-#define MDIO_WAIT_TIMES 30
-
-/* MII PHY Status Register */
-#define REG_PHY_STATUS 0x1418
-
-/* BIST Control and Status Register0 (for the Packet Memory) */
-#define REG_BIST0_CTRL 0x141c
-#define BIST0_NOW 0x1
-#define BIST0_SRAM_FAIL 0x2
-#define BIST0_FUSE_FLAG 0x4
-#define REG_BIST1_CTRL 0x1420
-#define BIST1_NOW 0x1
-#define BIST1_SRAM_FAIL 0x2
-#define BIST1_FUSE_FLAG 0x4
-
-/* MAC Control Register */
-#define REG_MAC_CTRL 0x1480
-#define MAC_CTRL_TX_EN 1
-#define MAC_CTRL_RX_EN 2
-#define MAC_CTRL_TX_FLOW 4
-#define MAC_CTRL_RX_FLOW 8
-#define MAC_CTRL_LOOPBACK 0x10
-#define MAC_CTRL_DUPLX 0x20
-#define MAC_CTRL_ADD_CRC 0x40
-#define MAC_CTRL_PAD 0x80
-#define MAC_CTRL_LENCHK 0x100
-#define MAC_CTRL_HUGE_EN 0x200
-#define MAC_CTRL_PRMLEN_SHIFT 10
-#define MAC_CTRL_PRMLEN_MASK 0xf
-#define MAC_CTRL_RMV_VLAN 0x4000
-#define MAC_CTRL_PROMIS_EN 0x8000
-#define MAC_CTRL_TX_PAUSE 0x10000
-#define MAC_CTRL_SCNT 0x20000
-#define MAC_CTRL_SRST_TX 0x40000
-#define MAC_CTRL_TX_SIMURST 0x80000
-#define MAC_CTRL_SPEED_SHIFT 20
-#define MAC_CTRL_SPEED_MASK 0x300000
-#define MAC_CTRL_SPEED_1000 2
-#define MAC_CTRL_SPEED_10_100 1
-#define MAC_CTRL_DBG_TX_BKPRESURE 0x400000
-#define MAC_CTRL_TX_HUGE 0x800000
-#define MAC_CTRL_RX_CHKSUM_EN 0x1000000
-#define MAC_CTRL_MC_ALL_EN 0x2000000
-#define MAC_CTRL_BC_EN 0x4000000
-#define MAC_CTRL_DBG 0x8000000
-
-/* MAC IPG/IFG Control Register */
-#define REG_MAC_IPG_IFG 0x1484
-#define MAC_IPG_IFG_IPGT_SHIFT 0
-#define MAC_IPG_IFG_IPGT_MASK 0x7f
-#define MAC_IPG_IFG_MIFG_SHIFT 8
-#define MAC_IPG_IFG_MIFG_MASK 0xff
-#define MAC_IPG_IFG_IPGR1_SHIFT 16
-#define MAC_IPG_IFG_IPGR1_MASK 0x7f
-#define MAC_IPG_IFG_IPGR2_SHIFT 24
-#define MAC_IPG_IFG_IPGR2_MASK 0x7f
-
-/* MAC STATION ADDRESS */
-#define REG_MAC_STA_ADDR 0x1488
-
-/* Hash table for multicast address */
-#define REG_RX_HASH_TABLE 0x1490
-
-/* MAC Half-Duplex Control Register */
-#define REG_MAC_HALF_DUPLX_CTRL 0x1498
-#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0
-#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff
-#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12
-#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf
-#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000
-#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000
-#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000
-#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000
-#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20
-#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf
-#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24
-#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf
-
-/* Maximum Frame Length Control Register */
-#define REG_MTU 0x149c
-
-/* Wake-On-Lan control register */
-#define REG_WOL_CTRL 0x14a0
-#define WOL_PATTERN_EN 0x00000001
-#define WOL_PATTERN_PME_EN 0x00000002
-#define WOL_MAGIC_EN 0x00000004
-#define WOL_MAGIC_PME_EN 0x00000008
-#define WOL_LINK_CHG_EN 0x00000010
-#define WOL_LINK_CHG_PME_EN 0x00000020
-#define WOL_PATTERN_ST 0x00000100
-#define WOL_MAGIC_ST 0x00000200
-#define WOL_LINKCHG_ST 0x00000400
-#define WOL_CLK_SWITCH_EN 0x00008000
-#define WOL_PT0_EN 0x00010000
-#define WOL_PT1_EN 0x00020000
-#define WOL_PT2_EN 0x00040000
-#define WOL_PT3_EN 0x00080000
-#define WOL_PT4_EN 0x00100000
-#define WOL_PT5_EN 0x00200000
-#define WOL_PT6_EN 0x00400000
-
-/* WOL Length ( 2 DWORD ) */
-#define REG_WOL_PATTERN_LEN 0x14a4
-#define WOL_PT_LEN_MASK 0x7f
-#define WOL_PT0_LEN_SHIFT 0
-#define WOL_PT1_LEN_SHIFT 8
-#define WOL_PT2_LEN_SHIFT 16
-#define WOL_PT3_LEN_SHIFT 24
-#define WOL_PT4_LEN_SHIFT 0
-#define WOL_PT5_LEN_SHIFT 8
-#define WOL_PT6_LEN_SHIFT 16
-
-/* Internal SRAM Partition Register */
-#define REG_SRAM_RFD_ADDR 0x1500
-#define REG_SRAM_RFD_LEN (REG_SRAM_RFD_ADDR+ 4)
-#define REG_SRAM_RRD_ADDR (REG_SRAM_RFD_ADDR+ 8)
-#define REG_SRAM_RRD_LEN (REG_SRAM_RFD_ADDR+12)
-#define REG_SRAM_TPD_ADDR (REG_SRAM_RFD_ADDR+16)
-#define REG_SRAM_TPD_LEN (REG_SRAM_RFD_ADDR+20)
-#define REG_SRAM_TRD_ADDR (REG_SRAM_RFD_ADDR+24)
-#define REG_SRAM_TRD_LEN (REG_SRAM_RFD_ADDR+28)
-#define REG_SRAM_RXF_ADDR (REG_SRAM_RFD_ADDR+32)
-#define REG_SRAM_RXF_LEN (REG_SRAM_RFD_ADDR+36)
-#define REG_SRAM_TXF_ADDR (REG_SRAM_RFD_ADDR+40)
-#define REG_SRAM_TXF_LEN (REG_SRAM_RFD_ADDR+44)
-#define REG_SRAM_TCPH_PATH_ADDR (REG_SRAM_RFD_ADDR+48)
-#define SRAM_TCPH_ADDR_MASK 0x0fff
-#define SRAM_TCPH_ADDR_SHIFT 0
-#define SRAM_PATH_ADDR_MASK 0x0fff
-#define SRAM_PATH_ADDR_SHIFT 16
-
-/* Load Ptr Register */
-#define REG_LOAD_PTR (REG_SRAM_RFD_ADDR+52)
-
-/* Descriptor Control register */
-#define REG_DESC_BASE_ADDR_HI 0x1540
-#define REG_DESC_RFD_ADDR_LO (REG_DESC_BASE_ADDR_HI+4)
-#define REG_DESC_RRD_ADDR_LO (REG_DESC_BASE_ADDR_HI+8)
-#define REG_DESC_TPD_ADDR_LO (REG_DESC_BASE_ADDR_HI+12)
-#define REG_DESC_CMB_ADDR_LO (REG_DESC_BASE_ADDR_HI+16)
-#define REG_DESC_SMB_ADDR_LO (REG_DESC_BASE_ADDR_HI+20)
-#define REG_DESC_RFD_RRD_RING_SIZE (REG_DESC_BASE_ADDR_HI+24)
-#define DESC_RFD_RING_SIZE_MASK 0x7ff
-#define DESC_RFD_RING_SIZE_SHIFT 0
-#define DESC_RRD_RING_SIZE_MASK 0x7ff
-#define DESC_RRD_RING_SIZE_SHIFT 16
-#define REG_DESC_TPD_RING_SIZE (REG_DESC_BASE_ADDR_HI+28)
-#define DESC_TPD_RING_SIZE_MASK 0x3ff
-#define DESC_TPD_RING_SIZE_SHIFT 0
-
-/* TXQ Control Register */
-#define REG_TXQ_CTRL 0x1580
-#define TXQ_CTRL_TPD_BURST_NUM_SHIFT 0
-#define TXQ_CTRL_TPD_BURST_NUM_MASK 0x1f
-#define TXQ_CTRL_EN 0x20
-#define TXQ_CTRL_ENH_MODE 0x40
-#define TXQ_CTRL_TPD_FETCH_TH_SHIFT 8
-#define TXQ_CTRL_TPD_FETCH_TH_MASK 0x3f
-#define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16
-#define TXQ_CTRL_TXF_BURST_NUM_MASK 0xffff
-
-/* Jumbo packet Threshold for task offload */
-#define REG_TX_JUMBO_TASK_TH_TPD_IPG 0x1584
-#define TX_JUMBO_TASK_TH_MASK 0x7ff
-#define TX_JUMBO_TASK_TH_SHIFT 0
-#define TX_TPD_MIN_IPG_MASK 0x1f
-#define TX_TPD_MIN_IPG_SHIFT 16
-
-/* RXQ Control Register */
-#define REG_RXQ_CTRL 0x15a0
-#define RXQ_CTRL_RFD_BURST_NUM_SHIFT 0
-#define RXQ_CTRL_RFD_BURST_NUM_MASK 0xff
-#define RXQ_CTRL_RRD_BURST_THRESH_SHIFT 8
-#define RXQ_CTRL_RRD_BURST_THRESH_MASK 0xff
-#define RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT 16
-#define RXQ_CTRL_RFD_PREF_MIN_IPG_MASK 0x1f
-#define RXQ_CTRL_CUT_THRU_EN 0x40000000
-#define RXQ_CTRL_EN 0x80000000
-
-/* Rx jumbo packet threshold and rrd retirement timer */
-#define REG_RXQ_JMBOSZ_RRDTIM (REG_RXQ_CTRL+ 4)
-#define RXQ_JMBOSZ_TH_MASK 0x7ff
-#define RXQ_JMBOSZ_TH_SHIFT 0
-#define RXQ_JMBO_LKAH_MASK 0xf
-#define RXQ_JMBO_LKAH_SHIFT 11
-#define RXQ_RRD_TIMER_MASK 0xffff
-#define RXQ_RRD_TIMER_SHIFT 16
-
-/* RFD flow control register */
-#define REG_RXQ_RXF_PAUSE_THRESH (REG_RXQ_CTRL+ 8)
-#define RXQ_RXF_PAUSE_TH_HI_SHIFT 16
-#define RXQ_RXF_PAUSE_TH_HI_MASK 0xfff
-#define RXQ_RXF_PAUSE_TH_LO_SHIFT 0
-#define RXQ_RXF_PAUSE_TH_LO_MASK 0xfff
-
-/* RRD flow control register */
-#define REG_RXQ_RRD_PAUSE_THRESH (REG_RXQ_CTRL+12)
-#define RXQ_RRD_PAUSE_TH_HI_SHIFT 0
-#define RXQ_RRD_PAUSE_TH_HI_MASK 0xfff
-#define RXQ_RRD_PAUSE_TH_LO_SHIFT 16
-#define RXQ_RRD_PAUSE_TH_LO_MASK 0xfff
-
-/* DMA Engine Control Register */
-#define REG_DMA_CTRL 0x15c0
-#define DMA_CTRL_DMAR_IN_ORDER 0x1
-#define DMA_CTRL_DMAR_ENH_ORDER 0x2
-#define DMA_CTRL_DMAR_OUT_ORDER 0x4
-#define DMA_CTRL_RCB_VALUE 0x8
-#define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
-#define DMA_CTRL_DMAR_BURST_LEN_MASK 7
-#define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
-#define DMA_CTRL_DMAW_BURST_LEN_MASK 7
-#define DMA_CTRL_DMAR_EN 0x400
-#define DMA_CTRL_DMAW_EN 0x800
-
-/* CMB/SMB Control Register */
-#define REG_CSMB_CTRL 0x15d0
-#define CSMB_CTRL_CMB_NOW 1
-#define CSMB_CTRL_SMB_NOW 2
-#define CSMB_CTRL_CMB_EN 4
-#define CSMB_CTRL_SMB_EN 8
-
-/* CMB DMA Write Threshold Register */
-#define REG_CMB_WRITE_TH (REG_CSMB_CTRL+ 4)
-#define CMB_RRD_TH_SHIFT 0
-#define CMB_RRD_TH_MASK 0x7ff
-#define CMB_TPD_TH_SHIFT 16
-#define CMB_TPD_TH_MASK 0x7ff
-
-/* RX/TX count-down timer to trigger CMB-write. 2us resolution. */
-#define REG_CMB_WRITE_TIMER (REG_CSMB_CTRL+ 8)
-#define CMB_RX_TM_SHIFT 0
-#define CMB_RX_TM_MASK 0xffff
-#define CMB_TX_TM_SHIFT 16
-#define CMB_TX_TM_MASK 0xffff
-
-/* Number of packet received since last CMB write */
-#define REG_CMB_RX_PKT_CNT (REG_CSMB_CTRL+12)
-
-/* Number of packet transmitted since last CMB write */
-#define REG_CMB_TX_PKT_CNT (REG_CSMB_CTRL+16)
-
-/* SMB auto DMA timer register */
-#define REG_SMB_TIMER (REG_CSMB_CTRL+20)
-
-/* Mailbox Register */
-#define REG_MAILBOX 0x15f0
-#define MB_RFD_PROD_INDX_SHIFT 0
-#define MB_RFD_PROD_INDX_MASK 0x7ff
-#define MB_RRD_CONS_INDX_SHIFT 11
-#define MB_RRD_CONS_INDX_MASK 0x7ff
-#define MB_TPD_PROD_INDX_SHIFT 22
-#define MB_TPD_PROD_INDX_MASK 0x3ff
-
-/* Interrupt Status Register */
-#define REG_ISR 0x1600
-#define ISR_SMB 1
-#define ISR_TIMER 2
-#define ISR_MANUAL 4
-#define ISR_RXF_OV 8
-#define ISR_RFD_UNRUN 0x10
-#define ISR_RRD_OV 0x20
-#define ISR_TXF_UNRUN 0x40
-#define ISR_LINK 0x80
-#define ISR_HOST_RFD_UNRUN 0x100
-#define ISR_HOST_RRD_OV 0x200
-#define ISR_DMAR_TO_RST 0x400
-#define ISR_DMAW_TO_RST 0x800
-#define ISR_GPHY 0x1000
-#define ISR_RX_PKT 0x10000
-#define ISR_TX_PKT 0x20000
-#define ISR_TX_DMA 0x40000
-#define ISR_RX_DMA 0x80000
-#define ISR_CMB_RX 0x100000
-#define ISR_CMB_TX 0x200000
-#define ISR_MAC_RX 0x400000
-#define ISR_MAC_TX 0x800000
-#define ISR_UR_DETECTED 0x1000000
-#define ISR_FERR_DETECTED 0x2000000
-#define ISR_NFERR_DETECTED 0x4000000
-#define ISR_CERR_DETECTED 0x8000000
-#define ISR_PHY_LINKDOWN 0x10000000
-#define ISR_DIS_SMB 0x20000000
-#define ISR_DIS_DMA 0x40000000
-#define ISR_DIS_INT 0x80000000
-
-/* Interrupt Mask Register */
-#define REG_IMR 0x1604
-
-/* Normal Interrupt mask */
-#define IMR_NORMAL_MASK (\
- ISR_SMB |\
- ISR_GPHY |\
- ISR_PHY_LINKDOWN|\
- ISR_DMAR_TO_RST |\
- ISR_DMAW_TO_RST |\
- ISR_CMB_TX |\
- ISR_CMB_RX )
-
-/* Debug Interrupt Mask (enable all interrupt) */
-#define IMR_DEBUG_MASK (\
- ISR_SMB |\
- ISR_TIMER |\
- ISR_MANUAL |\
- ISR_RXF_OV |\
- ISR_RFD_UNRUN |\
- ISR_RRD_OV |\
- ISR_TXF_UNRUN |\
- ISR_LINK |\
- ISR_CMB_TX |\
- ISR_CMB_RX |\
- ISR_RX_PKT |\
- ISR_TX_PKT |\
- ISR_MAC_RX |\
- ISR_MAC_TX )
-
-/* Interrupt Status Register */
-#define REG_RFD_RRD_IDX 0x1800
-#define REG_TPD_IDX 0x1804
-
-/* MII definition */
-/* PHY Common Register */
-#define MII_AT001_CR 0x09
-#define MII_AT001_SR 0x0A
-#define MII_AT001_ESR 0x0F
-#define MII_AT001_PSCR 0x10
-#define MII_AT001_PSSR 0x11
-
-/* PHY Control Register */
-#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
-#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
-#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
-#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
-#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
-#define MII_CR_POWER_DOWN 0x0800 /* Power down */
-#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
-#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
-#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
-#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
-#define MII_CR_SPEED_MASK 0x2040
-#define MII_CR_SPEED_1000 0x0040
-#define MII_CR_SPEED_100 0x2000
-#define MII_CR_SPEED_10 0x0000
-
-/* PHY Status Register */
-#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
-#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
-#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
-#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
-#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
-#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
-#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
-#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
-#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
-#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
-#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
-#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
-#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
-#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
-#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
-
-/* Link partner ability register. */
-#define MII_LPA_SLCT 0x001f /* Same as advertise selector */
-#define MII_LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
-#define MII_LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
-#define MII_LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
-#define MII_LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
-#define MII_LPA_100BASE4 0x0200 /* 100BASE-T4 */
-#define MII_LPA_PAUSE 0x0400 /* PAUSE */
-#define MII_LPA_ASYPAUSE 0x0800 /* Asymmetrical PAUSE */
-#define MII_LPA_RFAULT 0x2000 /* Link partner faulted */
-#define MII_LPA_LPACK 0x4000 /* Link partner acked us */
-#define MII_LPA_NPAGE 0x8000 /* Next page bit */
-
-/* Autoneg Advertisement Register */
-#define MII_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
-#define MII_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
-#define MII_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
-#define MII_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
-#define MII_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
-#define MII_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
-#define MII_AR_PAUSE 0x0400 /* Pause operation desired */
-#define MII_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
-#define MII_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
-#define MII_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
-#define MII_AR_SPEED_MASK 0x01E0
-#define MII_AR_DEFAULT_CAP_MASK 0x0DE0
-
-/* 1000BASE-T Control Register */
-#define MII_AT001_CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
-#define MII_AT001_CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
-#define MII_AT001_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port, 0=DTE device */
-#define MII_AT001_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master, 0=Configure PHY as Slave */
-#define MII_AT001_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value, 0=Automatic Master/Slave config */
-#define MII_AT001_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
-#define MII_AT001_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
-#define MII_AT001_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
-#define MII_AT001_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
-#define MII_AT001_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
-#define MII_AT001_CR_1000T_SPEED_MASK 0x0300
-#define MII_AT001_CR_1000T_DEFAULT_CAP_MASK 0x0300
-
-/* 1000BASE-T Status Register */
-#define MII_AT001_SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
-#define MII_AT001_SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
-#define MII_AT001_SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
-#define MII_AT001_SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
-#define MII_AT001_SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
-#define MII_AT001_SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
-#define MII_AT001_SR_1000T_REMOTE_RX_STATUS_SHIFT 12
-#define MII_AT001_SR_1000T_LOCAL_RX_STATUS_SHIFT 13
-
-/* Extended Status Register */
-#define MII_AT001_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
-#define MII_AT001_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
-#define MII_AT001_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
-#define MII_AT001_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
-
-/* AT001 PHY Specific Control Register */
-#define MII_AT001_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
-#define MII_AT001_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
-#define MII_AT001_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
-#define MII_AT001_PSCR_MAC_POWERDOWN 0x0008
-#define MII_AT001_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, 0=CLK125 toggling */
-#define MII_AT001_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5, Manual MDI configuration */
-#define MII_AT001_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
-#define MII_AT001_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
-#define MII_AT001_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled all speeds. */
-#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE 0x0080 /* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T RX Threshold), 0=Normal 10BASE-T RX Threshold */
-#define MII_AT001_PSCR_MII_5BIT_ENABLE 0x0100 /* 1=5-Bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
-#define MII_AT001_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
-#define MII_AT001_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
-#define MII_AT001_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
-#define MII_AT001_PSCR_POLARITY_REVERSAL_SHIFT 1
-#define MII_AT001_PSCR_AUTO_X_MODE_SHIFT 5
-#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
-
-/* AT001 PHY Specific Status Register */
-#define MII_AT001_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
-#define MII_AT001_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
-#define MII_AT001_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
-#define MII_AT001_PSSR_10MBS 0x0000 /* 00=10Mbs */
-#define MII_AT001_PSSR_100MBS 0x4000 /* 01=100Mbs */
-#define MII_AT001_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
-
-/* PCI Command Register Bit Definitions */
-#define PCI_REG_COMMAND 0x04 /* PCI Command Register */
-#define CMD_IO_SPACE 0x0001
-#define CMD_MEMORY_SPACE 0x0002
-#define CMD_BUS_MASTER 0x0004
-
-/* Wake Up Filter Control */
-#define ATL1_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
-#define ATL1_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
-#define ATL1_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
-#define ATL1_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */
-#define ATL1_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
-
-/* Error Codes */
-#define ATL1_SUCCESS 0
-#define ATL1_ERR_EEPROM 1
-#define ATL1_ERR_PHY 2
-#define ATL1_ERR_CONFIG 3
-#define ATL1_ERR_PARAM 4
-#define ATL1_ERR_MAC_TYPE 5
-#define ATL1_ERR_PHY_TYPE 6
-#define ATL1_ERR_PHY_SPEED 7
-#define ATL1_ERR_PHY_RES 8
-
-#define SPEED_0 0xffff
-#define SPEED_10 10
-#define SPEED_100 100
-#define SPEED_1000 1000
-#define HALF_DUPLEX 1
-#define FULL_DUPLEX 2
-
-#define MEDIA_TYPE_AUTO_SENSOR 0
-#define MEDIA_TYPE_1000M_FULL 1
-#define MEDIA_TYPE_100M_FULL 2
-#define MEDIA_TYPE_100M_HALF 3
-#define MEDIA_TYPE_10M_FULL 4
-#define MEDIA_TYPE_10M_HALF 5
-
-#define ADVERTISE_10_HALF 0x0001
-#define ADVERTISE_10_FULL 0x0002
-#define ADVERTISE_100_HALF 0x0004
-#define ADVERTISE_100_FULL 0x0008
-#define ADVERTISE_1000_HALF 0x0010
-#define ADVERTISE_1000_FULL 0x0020
-#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
-#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds */
-#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds */
-
-#define MAX_JUMBO_FRAME_SIZE 0x2800
-
-#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
-#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
-
-/* For checksumming , the sum of all words in the EEPROM should equal 0xBABA */
-#define EEPROM_SUM 0xBABA
-
-#define ATL1_EEDUMP_LEN 48
-
-/* Statistics counters collected by the MAC */
-struct stats_msg_block {
- /* rx */
- u32 rx_ok; /* The number of good packet received. */
- u32 rx_bcast; /* The number of good broadcast packet received. */
- u32 rx_mcast; /* The number of good multicast packet received. */
- u32 rx_pause; /* The number of Pause packet received. */
- u32 rx_ctrl; /* The number of Control packet received other than Pause frame. */
- u32 rx_fcs_err; /* The number of packets with bad FCS. */
- u32 rx_len_err; /* The number of packets with mismatch of length field and actual size. */
- u32 rx_byte_cnt; /* The number of bytes of good packet received. FCS is NOT included. */
- u32 rx_runt; /* The number of packets received that are less than 64 byte long and with good FCS. */
- u32 rx_frag; /* The number of packets received that are less than 64 byte long and with bad FCS. */
- u32 rx_sz_64; /* The number of good and bad packets received that are 64 byte long. */
- u32 rx_sz_65_127; /* The number of good and bad packets received that are between 65 and 127-byte long. */
- u32 rx_sz_128_255; /* The number of good and bad packets received that are between 128 and 255-byte long. */
- u32 rx_sz_256_511; /* The number of good and bad packets received that are between 256 and 511-byte long. */
- u32 rx_sz_512_1023; /* The number of good and bad packets received that are between 512 and 1023-byte long. */
- u32 rx_sz_1024_1518; /* The number of good and bad packets received that are between 1024 and 1518-byte long. */
- u32 rx_sz_1519_max; /* The number of good and bad packets received that are between 1519-byte and MTU. */
- u32 rx_sz_ov; /* The number of good and bad packets received that are more than MTU size Å¡C truncated by Selene. */
- u32 rx_rxf_ov; /* The number of frame dropped due to occurrence of RX FIFO overflow. */
- u32 rx_rrd_ov; /* The number of frame dropped due to occurrence of RRD overflow. */
- u32 rx_align_err; /* Alignment Error */
- u32 rx_bcast_byte_cnt; /* The byte count of broadcast packet received, excluding FCS. */
- u32 rx_mcast_byte_cnt; /* The byte count of multicast packet received, excluding FCS. */
- u32 rx_err_addr; /* The number of packets dropped due to address filtering. */
-
- /* tx */
- u32 tx_ok; /* The number of good packet transmitted. */
- u32 tx_bcast; /* The number of good broadcast packet transmitted. */
- u32 tx_mcast; /* The number of good multicast packet transmitted. */
- u32 tx_pause; /* The number of Pause packet transmitted. */
- u32 tx_exc_defer; /* The number of packets transmitted with excessive deferral. */
- u32 tx_ctrl; /* The number of packets transmitted is a control frame, excluding Pause frame. */
- u32 tx_defer; /* The number of packets transmitted that is deferred. */
- u32 tx_byte_cnt; /* The number of bytes of data transmitted. FCS is NOT included. */
- u32 tx_sz_64; /* The number of good and bad packets transmitted that are 64 byte long. */
- u32 tx_sz_65_127; /* The number of good and bad packets transmitted that are between 65 and 127-byte long. */
- u32 tx_sz_128_255; /* The number of good and bad packets transmitted that are between 128 and 255-byte long. */
- u32 tx_sz_256_511; /* The number of good and bad packets transmitted that are between 256 and 511-byte long. */
- u32 tx_sz_512_1023; /* The number of good and bad packets transmitted that are between 512 and 1023-byte long. */
- u32 tx_sz_1024_1518; /* The number of good and bad packets transmitted that are between 1024 and 1518-byte long. */
- u32 tx_sz_1519_max; /* The number of good and bad packets transmitted that are between 1519-byte and MTU. */
- u32 tx_1_col; /* The number of packets subsequently transmitted successfully with a single prior collision. */
- u32 tx_2_col; /* The number of packets subsequently transmitted successfully with multiple prior collisions. */
- u32 tx_late_col; /* The number of packets transmitted with late collisions. */
- u32 tx_abort_col; /* The number of transmit packets aborted due to excessive collisions. */
- u32 tx_underrun; /* The number of transmit packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */
- u32 tx_rd_eop; /* The number of times that read beyond the EOP into the next frame area when TRD was not written timely */
- u32 tx_len_err; /* The number of transmit packets with length field does NOT match the actual frame size. */
- u32 tx_trunc; /* The number of transmit packets truncated due to size exceeding MTU. */
- u32 tx_bcast_byte; /* The byte count of broadcast packet transmitted, excluding FCS. */
- u32 tx_mcast_byte; /* The byte count of multicast packet transmitted, excluding FCS. */
- u32 smb_updated; /* 1: SMB Updated. This is used by software as the indication of the statistics update.
- * Software should clear this bit as soon as retrieving the statistics information. */
-};
-
-/* Coalescing Message Block */
-struct coals_msg_block {
- u32 int_stats; /* interrupt status */
- u16 rrd_prod_idx; /* TRD Producer Index. */
- u16 rfd_cons_idx; /* RFD Consumer Index. */
- u16 update; /* Selene sets this bit every time it DMA the CMB to host memory.
- * Software supposes to clear this bit when CMB information is processed. */
- u16 tpd_cons_idx; /* TPD Consumer Index. */
-};
-
-/* RRD descriptor */
-struct rx_return_desc {
- u8 num_buf; /* Number of RFD buffers used by the received packet */
- u8 resved;
- u16 buf_indx; /* RFD Index of the first buffer */
- union {
- u32 valid;
- struct {
- u16 rx_chksum;
- u16 pkt_size;
- } xsum_sz;
- } xsz;
-
- u16 pkt_flg; /* Packet flags */
- u16 err_flg; /* Error flags */
- u16 resved2;
- u16 vlan_tag; /* VLAN TAG */
-};
-
-#define PACKET_FLAG_ETH_TYPE 0x0080
-#define PACKET_FLAG_VLAN_INS 0x0100
-#define PACKET_FLAG_ERR 0x0200
-#define PACKET_FLAG_IPV4 0x0400
-#define PACKET_FLAG_UDP 0x0800
-#define PACKET_FLAG_TCP 0x1000
-#define PACKET_FLAG_BCAST 0x2000
-#define PACKET_FLAG_MCAST 0x4000
-#define PACKET_FLAG_PAUSE 0x8000
-
-#define ERR_FLAG_CRC 0x0001
-#define ERR_FLAG_CODE 0x0002
-#define ERR_FLAG_DRIBBLE 0x0004
-#define ERR_FLAG_RUNT 0x0008
-#define ERR_FLAG_OV 0x0010
-#define ERR_FLAG_TRUNC 0x0020
-#define ERR_FLAG_IP_CHKSUM 0x0040
-#define ERR_FLAG_L4_CHKSUM 0x0080
-#define ERR_FLAG_LEN 0x0100
-#define ERR_FLAG_DES_ADDR 0x0200
-
-/* RFD descriptor */
-struct rx_free_desc {
- __le64 buffer_addr; /* Address of the descriptor's data buffer */
- __le16 buf_len; /* Size of the receive buffer in host memory, in byte */
- u16 coalese; /* Update consumer index to host after the reception of this frame */
- /* __attribute__ ((packed)) is required */
-} __attribute__ ((packed));
-
-/* tsopu defines */
-#define TSO_PARAM_BUFLEN_MASK 0x3FFF
-#define TSO_PARAM_BUFLEN_SHIFT 0
-#define TSO_PARAM_DMAINT_MASK 0x0001
-#define TSO_PARAM_DMAINT_SHIFT 14
-#define TSO_PARAM_PKTNT_MASK 0x0001
-#define TSO_PARAM_PKTINT_SHIFT 15
-#define TSO_PARAM_VLANTAG_MASK 0xFFFF
-#define TSO_PARAM_VLAN_SHIFT 16
-
-/* tsopl defines */
-#define TSO_PARAM_EOP_MASK 0x0001
-#define TSO_PARAM_EOP_SHIFT 0
-#define TSO_PARAM_COALESCE_MASK 0x0001
-#define TSO_PARAM_COALESCE_SHIFT 1
-#define TSO_PARAM_INSVLAG_MASK 0x0001
-#define TSO_PARAM_INSVLAG_SHIFT 2
-#define TSO_PARAM_CUSTOMCKSUM_MASK 0x0001
-#define TSO_PARAM_CUSTOMCKSUM_SHIFT 3
-#define TSO_PARAM_SEGMENT_MASK 0x0001
-#define TSO_PARAM_SEGMENT_SHIFT 4
-#define TSO_PARAM_IPCKSUM_MASK 0x0001
-#define TSO_PARAM_IPCKSUM_SHIFT 5
-#define TSO_PARAM_TCPCKSUM_MASK 0x0001
-#define TSO_PARAM_TCPCKSUM_SHIFT 6
-#define TSO_PARAM_UDPCKSUM_MASK 0x0001
-#define TSO_PARAM_UDPCKSUM_SHIFT 7
-#define TSO_PARAM_VLANTAGGED_MASK 0x0001
-#define TSO_PARAM_VLANTAGGED_SHIFT 8
-#define TSO_PARAM_ETHTYPE_MASK 0x0001
-#define TSO_PARAM_ETHTYPE_SHIFT 9
-#define TSO_PARAM_IPHL_MASK 0x000F
-#define TSO_PARAM_IPHL_SHIFT 10
-#define TSO_PARAM_TCPHDRLEN_MASK 0x000F
-#define TSO_PARAM_TCPHDRLEN_SHIFT 14
-#define TSO_PARAM_HDRFLAG_MASK 0x0001
-#define TSO_PARAM_HDRFLAG_SHIFT 18
-#define TSO_PARAM_MSS_MASK 0x1FFF
-#define TSO_PARAM_MSS_SHIFT 19
-
-/* csumpu defines */
-#define CSUM_PARAM_BUFLEN_MASK 0x3FFF
-#define CSUM_PARAM_BUFLEN_SHIFT 0
-#define CSUM_PARAM_DMAINT_MASK 0x0001
-#define CSUM_PARAM_DMAINT_SHIFT 14
-#define CSUM_PARAM_PKTINT_MASK 0x0001
-#define CSUM_PARAM_PKTINT_SHIFT 15
-#define CSUM_PARAM_VALANTAG_MASK 0xFFFF
-#define CSUM_PARAM_VALAN_SHIFT 16
-
-/* csumpl defines*/
-#define CSUM_PARAM_EOP_MASK 0x0001
-#define CSUM_PARAM_EOP_SHIFT 0
-#define CSUM_PARAM_COALESCE_MASK 0x0001
-#define CSUM_PARAM_COALESCE_SHIFT 1
-#define CSUM_PARAM_INSVLAG_MASK 0x0001
-#define CSUM_PARAM_INSVLAG_SHIFT 2
-#define CSUM_PARAM_CUSTOMCKSUM_MASK 0x0001
-#define CSUM_PARAM_CUSTOMCKSUM_SHIFT 3
-#define CSUM_PARAM_SEGMENT_MASK 0x0001
-#define CSUM_PARAM_SEGMENT_SHIFT 4
-#define CSUM_PARAM_IPCKSUM_MASK 0x0001
-#define CSUM_PARAM_IPCKSUM_SHIFT 5
-#define CSUM_PARAM_TCPCKSUM_MASK 0x0001
-#define CSUM_PARAM_TCPCKSUM_SHIFT 6
-#define CSUM_PARAM_UDPCKSUM_MASK 0x0001
-#define CSUM_PARAM_UDPCKSUM_SHIFT 7
-#define CSUM_PARAM_VLANTAGGED_MASK 0x0001
-#define CSUM_PARAM_VLANTAGGED_SHIFT 8
-#define CSUM_PARAM_ETHTYPE_MASK 0x0001
-#define CSUM_PARAM_ETHTYPE_SHIFT 9
-#define CSUM_PARAM_IPHL_MASK 0x000F
-#define CSUM_PARAM_IPHL_SHIFT 10
-#define CSUM_PARAM_PLOADOFFSET_MASK 0x00FF
-#define CSUM_PARAM_PLOADOFFSET_SHIFT 16
-#define CSUM_PARAM_XSUMOFFSET_MASK 0x00FF
-#define CSUM_PARAM_XSUMOFFSET_SHIFT 24
-
-/* TPD descriptor */
-struct tso_param {
- /* The order of these declarations is important -- don't change it */
- u32 tsopu; /* tso_param upper word */
- u32 tsopl; /* tso_param lower word */
-};
-
-struct csum_param {
- /* The order of these declarations is important -- don't change it */
- u32 csumpu; /* csum_param upper word */
- u32 csumpl; /* csum_param lower word */
-};
-
-union tpd_descr {
- u64 data;
- struct csum_param csum;
- struct tso_param tso;
-};
-
-struct tx_packet_desc {
- __le64 buffer_addr;
- union tpd_descr desc;
-};
-
-/* DMA Order Settings */
-enum atl1_dma_order {
- atl1_dma_ord_in = 1,
- atl1_dma_ord_enh = 2,
- atl1_dma_ord_out = 4
-};
-
-enum atl1_dma_rcb {
- atl1_rcb_64 = 0,
- atl1_rcb_128 = 1
-};
-
-enum atl1_dma_req_block {
- atl1_dma_req_128 = 0,
- atl1_dma_req_256 = 1,
- atl1_dma_req_512 = 2,
- atl1_dma_req_1024 = 3,
- atl1_dma_req_2048 = 4,
- atl1_dma_req_4096 = 5
-};
-
-struct atl1_spi_flash_dev {
- const char *manu_name; /* manufacturer id */
- /* op-code */
- u8 cmd_wrsr;
- u8 cmd_read;
- u8 cmd_program;
- u8 cmd_wren;
- u8 cmd_wrdi;
- u8 cmd_rdsr;
- u8 cmd_rdid;
- u8 cmd_sector_erase;
- u8 cmd_chip_erase;
-};
-
-#endif /* _ATL1_HW_H_ */
diff --git a/drivers/net/atlx/atl1_param.c b/drivers/net/atlx/atl1_param.c
deleted file mode 100644
index 4246bb9..0000000
--- a/drivers/net/atlx/atl1_param.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/*
- * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
- * Copyright(c) 2006 Chris Snook <csnook@redhat.com>
- * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
- *
- * Derived from Intel e1000 driver
- * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59
- * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#include <linux/types.h>
-#include <linux/moduleparam.h>
-#include <linux/pci.h>
-#include "atl1.h"
-
-/*
- * This is the only thing that needs to be changed to adjust the
- * maximum number of ports that the driver can manage.
- */
-#define ATL1_MAX_NIC 4
-
-#define OPTION_UNSET -1
-#define OPTION_DISABLED 0
-#define OPTION_ENABLED 1
-
-#define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET }
-
-/*
- * Interrupt Moderate Timer in units of 2 us
- *
- * Valid Range: 10-65535
- *
- * Default Value: 100 (200us)
- */
-static int __devinitdata int_mod_timer[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
-static int num_int_mod_timer = 0;
-module_param_array_named(int_mod_timer, int_mod_timer, int, &num_int_mod_timer, 0);
-MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer");
-
-/*
- * flash_vendor
- *
- * Valid Range: 0-2
- *
- * 0 - Atmel
- * 1 - SST
- * 2 - ST
- *
- * Default Value: 0
- */
-static int __devinitdata flash_vendor[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
-static int num_flash_vendor = 0;
-module_param_array_named(flash_vendor, flash_vendor, int, &num_flash_vendor, 0);
-MODULE_PARM_DESC(flash_vendor, "SPI flash vendor");
-
-#define DEFAULT_INT_MOD_CNT 100 /* 200us */
-#define MAX_INT_MOD_CNT 65000
-#define MIN_INT_MOD_CNT 50
-
-#define FLASH_VENDOR_DEFAULT 0
-#define FLASH_VENDOR_MIN 0
-#define FLASH_VENDOR_MAX 2
-
-struct atl1_option {
- enum { enable_option, range_option, list_option } type;
- char *name;
- char *err;
- int def;
- union {
- struct { /* range_option info */
- int min;
- int max;
- } r;
- struct { /* list_option info */
- int nr;
- struct atl1_opt_list {
- int i;
- char *str;
- } *p;
- } l;
- } arg;
-};
-
-static int __devinit atl1_validate_option(int *value, struct atl1_option *opt, struct pci_dev *pdev)
-{
- if (*value == OPTION_UNSET) {
- *value = opt->def;
- return 0;
- }
-
- switch (opt->type) {
- case enable_option:
- switch (*value) {
- case OPTION_ENABLED:
- dev_info(&pdev->dev, "%s enabled\n", opt->name);
- return 0;
- case OPTION_DISABLED:
- dev_info(&pdev->dev, "%s disabled\n", opt->name);
- return 0;
- }
- break;
- case range_option:
- if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
- dev_info(&pdev->dev, "%s set to %i\n", opt->name,
- *value);
- return 0;
- }
- break;
- case list_option:{
- int i;
- struct atl1_opt_list *ent;
-
- for (i = 0; i < opt->arg.l.nr; i++) {
- ent = &opt->arg.l.p[i];
- if (*value == ent->i) {
- if (ent->str[0] != '\0')
- dev_info(&pdev->dev, "%s\n",
- ent->str);
- return 0;
- }
- }
- }
- break;
-
- default:
- break;
- }
-
- dev_info(&pdev->dev, "invalid %s specified (%i) %s\n",
- opt->name, *value, opt->err);
- *value = opt->def;
- return -1;
-}
-
-/*
- * atl1_check_options - Range Checking for Command Line Parameters
- * @adapter: board private structure
- *
- * This routine checks all command line parameters for valid user
- * input. If an invalid value is given, or if no user specified
- * value exists, a default value is used. The final value is stored
- * in a variable in the adapter structure.
- */
-void __devinit atl1_check_options(struct atl1_adapter *adapter)
-{
- struct pci_dev *pdev = adapter->pdev;
- int bd = adapter->bd_number;
- if (bd >= ATL1_MAX_NIC) {
- dev_notice(&pdev->dev, "no configuration for board#%i\n", bd);
- dev_notice(&pdev->dev, "using defaults for all values\n");
- }
- { /* Interrupt Moderate Timer */
- struct atl1_option opt = {
- .type = range_option,
- .name = "Interrupt Moderator Timer",
- .err = "using default of "
- __MODULE_STRING(DEFAULT_INT_MOD_CNT),
- .def = DEFAULT_INT_MOD_CNT,
- .arg = {.r =
- {.min = MIN_INT_MOD_CNT,.max = MAX_INT_MOD_CNT}}
- };
- int val;
- if (num_int_mod_timer > bd) {
- val = int_mod_timer[bd];
- atl1_validate_option(&val, &opt, pdev);
- adapter->imt = (u16) val;
- } else
- adapter->imt = (u16) (opt.def);
- }
-
- { /* Flash Vendor */
- struct atl1_option opt = {
- .type = range_option,
- .name = "SPI Flash Vendor",
- .err = "using default of "
- __MODULE_STRING(FLASH_VENDOR_DEFAULT),
- .def = DEFAULT_INT_MOD_CNT,
- .arg = {.r =
- {.min = FLASH_VENDOR_MIN,.max =
- FLASH_VENDOR_MAX}}
- };
- int val;
- if (num_flash_vendor > bd) {
- val = flash_vendor[bd];
- atl1_validate_option(&val, &opt, pdev);
- adapter->hw.flash_vendor = (u8) val;
- } else
- adapter->hw.flash_vendor = (u8) (opt.def);
- }
-}
diff --git a/drivers/net/atlx/atlx.c b/drivers/net/atlx/atlx.c
new file mode 100644
index 0000000..4186326
--- /dev/null
+++ b/drivers/net/atlx/atlx.c
@@ -0,0 +1,433 @@
+/* atlx.c -- common functions for Attansic network drivers
+ *
+ * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
+ * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
+ * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
+ * Copyright(c) 2007 Atheros Corporation. All rights reserved.
+ *
+ * Derived from Intel e1000 driver
+ * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59
+ * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+/* Including this file like a header is a temporary hack, I promise. -- CHS */
+#ifndef ATLX_C
+#define ATLX_C
+
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/etherdevice.h>
+#include <linux/if.h>
+#include <linux/netdevice.h>
+#include <linux/socket.h>
+#include <linux/sockios.h>
+#include <linux/spinlock.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include <linux/workqueue.h>
+
+#include "atlx.h"
+
+static struct atlx_spi_flash_dev flash_table[] = {
+/* MFR_NAME WRSR READ PRGM WREN WRDI RDSR RDID SEC_ERS CHIP_ERS */
+ {"Atmel", 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62},
+ {"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60},
+ {"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7},
+};
+
+static int atlx_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
+{
+ switch (cmd) {
+ case SIOCGMIIPHY:
+ case SIOCGMIIREG:
+ case SIOCSMIIREG:
+ return atlx_mii_ioctl(netdev, ifr, cmd);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+/*
+ * atlx_set_mac - Change the Ethernet Address of the NIC
+ * @netdev: network interface device structure
+ * @p: pointer to an address structure
+ *
+ * Returns 0 on success, negative on failure
+ */
+static int atlx_set_mac(struct net_device *netdev, void *p)
+{
+ struct atlx_adapter *adapter = netdev_priv(netdev);
+ struct sockaddr *addr = p;
+
+ if (netif_running(netdev))
+ return -EBUSY;
+
+ if (!is_valid_ether_addr(addr->sa_data))
+ return -EADDRNOTAVAIL;
+
+ memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
+ memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
+
+ atlx_set_mac_addr(&adapter->hw);
+ return 0;
+}
+
+static void atlx_check_for_link(struct atlx_adapter *adapter)
+{
+ struct net_device *netdev = adapter->netdev;
+ u16 phy_data = 0;
+
+ spin_lock(&adapter->lock);
+ adapter->phy_timer_pending = false;
+ atlx_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
+ atlx_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
+ spin_unlock(&adapter->lock);
+
+ /* notify upper layer link down ASAP */
+ if (!(phy_data & BMSR_LSTATUS)) {
+ /* Link Down */
+ if (netif_carrier_ok(netdev)) {
+ /* old link state: Up */
+ dev_info(&adapter->pdev->dev, "%s link is down\n",
+ netdev->name);
+ adapter->link_speed = SPEED_0;
+ netif_carrier_off(netdev);
+ netif_stop_queue(netdev);
+ }
+ }
+ schedule_work(&adapter->link_chg_task);
+}
+
+/*
+ * atlx_set_multi - Multicast and Promiscuous mode set
+ * @netdev: network interface device structure
+ *
+ * The set_multi entry point is called whenever the multicast address
+ * list or the network interface flags are updated. This routine is
+ * responsible for configuring the hardware for proper multicast,
+ * promiscuous mode, and all-multi behavior.
+ */
+static void atlx_set_multi(struct net_device *netdev)
+{
+ struct atlx_adapter *adapter = netdev_priv(netdev);
+ struct atlx_hw *hw = &adapter->hw;
+ struct dev_mc_list *mc_ptr;
+ u32 rctl;
+ u32 hash_value;
+
+ /* Check for Promiscuous and All Multicast modes */
+ rctl = ioread32(hw->hw_addr + REG_MAC_CTRL);
+ if (netdev->flags & IFF_PROMISC)
+ rctl |= MAC_CTRL_PROMIS_EN;
+ else if (netdev->flags & IFF_ALLMULTI) {
+ rctl |= MAC_CTRL_MC_ALL_EN;
+ rctl &= ~MAC_CTRL_PROMIS_EN;
+ } else
+ rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
+
+ iowrite32(rctl, hw->hw_addr + REG_MAC_CTRL);
+
+ /* clear the old settings from the multicast hash table */
+ iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
+ iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
+
+ /* compute mc addresses' hash value ,and put it into hash table */
+ for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
+ hash_value = atlx_hash_mc_addr(hw, mc_ptr->dmi_addr);
+ atlx_hash_set(hw, hash_value);
+ }
+}
+
+/*
+ * atlx_irq_enable - Enable default interrupt generation settings
+ * @adapter: board private structure
+ */
+static void atlx_irq_enable(struct atlx_adapter *adapter)
+{
+ iowrite32(IMR_NORMAL_MASK, adapter->hw.hw_addr + REG_IMR);
+ ioread32(adapter->hw.hw_addr + REG_IMR);
+}
+
+/*
+ * atlx_irq_disable - Mask off interrupt generation on the NIC
+ * @adapter: board private structure
+ */
+static void atlx_irq_disable(struct atlx_adapter *adapter)
+{
+ iowrite32(0, adapter->hw.hw_addr + REG_IMR);
+ ioread32(adapter->hw.hw_addr + REG_IMR);
+ synchronize_irq(adapter->pdev->irq);
+}
+
+static void atlx_clear_phy_int(struct atlx_adapter *adapter)
+{
+ u16 phy_data;
+ unsigned long flags;
+
+ spin_lock_irqsave(&adapter->lock, flags);
+ atlx_read_phy_reg(&adapter->hw, 19, &phy_data);
+ spin_unlock_irqrestore(&adapter->lock, flags);
+}
+
+/*
+ * atlx_get_stats - Get System Network Statistics
+ * @netdev: network interface device structure
+ *
+ * Returns the address of the device statistics structure.
+ * The statistics are actually updated from the timer callback.
+ */
+static struct net_device_stats *atlx_get_stats(struct net_device *netdev)
+{
+ struct atlx_adapter *adapter = netdev_priv(netdev);
+ return &adapter->net_stats;
+}
+
+/*
+ * atlx_tx_timeout - Respond to a Tx Hang
+ * @netdev: network interface device structure
+ */
+static void atlx_tx_timeout(struct net_device *netdev)
+{
+ struct atlx_adapter *adapter = netdev_priv(netdev);
+ /* Do the reset outside of interrupt context */
+ schedule_work(&adapter->tx_timeout_task);
+}
+
+/*
+ * atlx_link_chg_task - deal with link change event Out of interrupt context
+ */
+static void atlx_link_chg_task(struct work_struct *work)
+{
+ struct atlx_adapter *adapter;
+ unsigned long flags;
+
+ adapter = container_of(work, struct atlx_adapter, link_chg_task);
+
+ spin_lock_irqsave(&adapter->lock, flags);
+ atlx_check_link(adapter);
+ spin_unlock_irqrestore(&adapter->lock, flags);
+}
+
+static void atlx_vlan_rx_register(struct net_device *netdev,
+ struct vlan_group *grp)
+{
+ struct atlx_adapter *adapter = netdev_priv(netdev);
+ unsigned long flags;
+ u32 ctrl;
+
+ spin_lock_irqsave(&adapter->lock, flags);
+ /* atlx_irq_disable(adapter); FIXME: confirm/remove */
+ adapter->vlgrp = grp;
+
+ if (grp) {
+ /* enable VLAN tag insert/strip */
+ ctrl = ioread32(adapter->hw.hw_addr + REG_MAC_CTRL);
+ ctrl |= MAC_CTRL_RMV_VLAN;
+ iowrite32(ctrl, adapter->hw.hw_addr + REG_MAC_CTRL);
+ } else {
+ /* disable VLAN tag insert/strip */
+ ctrl = ioread32(adapter->hw.hw_addr + REG_MAC_CTRL);
+ ctrl &= ~MAC_CTRL_RMV_VLAN;
+ iowrite32(ctrl, adapter->hw.hw_addr + REG_MAC_CTRL);
+ }
+
+ /* atlx_irq_enable(adapter); FIXME */
+ spin_unlock_irqrestore(&adapter->lock, flags);
+}
+
+static void atlx_restore_vlan(struct atlx_adapter *adapter)
+{
+ atlx_vlan_rx_register(adapter->netdev, adapter->vlgrp);
+}
+
+/*
+ * This is the only thing that needs to be changed to adjust the
+ * maximum number of ports that the driver can manage.
+ */
+#define ATL1_MAX_NIC 4
+
+#define OPTION_UNSET -1
+#define OPTION_DISABLED 0
+#define OPTION_ENABLED 1
+
+#define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET }
+
+/*
+ * Interrupt Moderate Timer in units of 2 us
+ *
+ * Valid Range: 10-65535
+ *
+ * Default Value: 100 (200us)
+ */
+static int __devinitdata int_mod_timer[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
+static int num_int_mod_timer;
+module_param_array_named(int_mod_timer, int_mod_timer, int,
+ &num_int_mod_timer, 0);
+MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer");
+
+/*
+ * flash_vendor
+ *
+ * Valid Range: 0-2
+ *
+ * 0 - Atmel
+ * 1 - SST
+ * 2 - ST
+ *
+ * Default Value: 0
+ */
+static int __devinitdata flash_vendor[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
+static int num_flash_vendor;
+module_param_array_named(flash_vendor, flash_vendor, int, &num_flash_vendor, 0);
+MODULE_PARM_DESC(flash_vendor, "SPI flash vendor");
+
+#define DEFAULT_INT_MOD_CNT 100 /* 200us */
+#define MAX_INT_MOD_CNT 65000
+#define MIN_INT_MOD_CNT 50
+
+#define FLASH_VENDOR_DEFAULT 0
+#define FLASH_VENDOR_MIN 0
+#define FLASH_VENDOR_MAX 2
+
+struct atl1_option {
+ enum { enable_option, range_option, list_option } type;
+ char *name;
+ char *err;
+ int def;
+ union {
+ struct { /* range_option info */
+ int min;
+ int max;
+ } r;
+ struct { /* list_option info */
+ int nr;
+ struct atl1_opt_list {
+ int i;
+ char *str;
+ } *p;
+ } l;
+ } arg;
+};
+
+static int __devinit atl1_validate_option(int *value, struct atl1_option *opt,
+ struct pci_dev *pdev)
+{
+ if (*value == OPTION_UNSET) {
+ *value = opt->def;
+ return 0;
+ }
+
+ switch (opt->type) {
+ case enable_option:
+ switch (*value) {
+ case OPTION_ENABLED:
+ dev_info(&pdev->dev, "%s enabled\n", opt->name);
+ return 0;
+ case OPTION_DISABLED:
+ dev_info(&pdev->dev, "%s disabled\n", opt->name);
+ return 0;
+ }
+ break;
+ case range_option:
+ if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
+ dev_info(&pdev->dev, "%s set to %i\n", opt->name,
+ *value);
+ return 0;
+ }
+ break;
+ case list_option:{
+ int i;
+ struct atl1_opt_list *ent;
+
+ for (i = 0; i < opt->arg.l.nr; i++) {
+ ent = &opt->arg.l.p[i];
+ if (*value == ent->i) {
+ if (ent->str[0] != '\0')
+ dev_info(&pdev->dev, "%s\n",
+ ent->str);
+ return 0;
+ }
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ dev_info(&pdev->dev, "invalid %s specified (%i) %s\n",
+ opt->name, *value, opt->err);
+ *value = opt->def;
+ return -1;
+}
+
+/*
+ * atl1_check_options - Range Checking for Command Line Parameters
+ * @adapter: board private structure
+ *
+ * This routine checks all command line parameters for valid user
+ * input. If an invalid value is given, or if no user specified
+ * value exists, a default value is used. The final value is stored
+ * in a variable in the adapter structure.
+ */
+void __devinit atl1_check_options(struct atl1_adapter *adapter)
+{
+ struct pci_dev *pdev = adapter->pdev;
+ int bd = adapter->bd_number;
+ if (bd >= ATL1_MAX_NIC) {
+ dev_notice(&pdev->dev, "no configuration for board#%i\n", bd);
+ dev_notice(&pdev->dev, "using defaults for all values\n");
+ }
+ { /* Interrupt Moderate Timer */
+ struct atl1_option opt = {
+ .type = range_option,
+ .name = "Interrupt Moderator Timer",
+ .err = "using default of "
+ __MODULE_STRING(DEFAULT_INT_MOD_CNT),
+ .def = DEFAULT_INT_MOD_CNT,
+ .arg = {.r = {.min = MIN_INT_MOD_CNT,
+ .max = MAX_INT_MOD_CNT} }
+ };
+ int val;
+ if (num_int_mod_timer > bd) {
+ val = int_mod_timer[bd];
+ atl1_validate_option(&val, &opt, pdev);
+ adapter->imt = (u16) val;
+ } else
+ adapter->imt = (u16) (opt.def);
+ }
+
+ { /* Flash Vendor */
+ struct atl1_option opt = {
+ .type = range_option,
+ .name = "SPI Flash Vendor",
+ .err = "using default of "
+ __MODULE_STRING(FLASH_VENDOR_DEFAULT),
+ .def = DEFAULT_INT_MOD_CNT,
+ .arg = {.r = {.min = FLASH_VENDOR_MIN,
+ .max = FLASH_VENDOR_MAX} }
+ };
+ int val;
+ if (num_flash_vendor > bd) {
+ val = flash_vendor[bd];
+ atl1_validate_option(&val, &opt, pdev);
+ adapter->hw.flash_vendor = (u8) val;
+ } else
+ adapter->hw.flash_vendor = (u8) (opt.def);
+ }
+}
+
+#endif /* ATLX_C */
diff --git a/drivers/net/atlx/atlx.h b/drivers/net/atlx/atlx.h
new file mode 100644
index 0000000..3be7c09
--- /dev/null
+++ b/drivers/net/atlx/atlx.h
@@ -0,0 +1,506 @@
+/* atlx_hw.h -- common hardware definitions for Attansic network drivers
+ *
+ * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
+ * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
+ * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
+ * Copyright(c) 2007 Atheros Corporation. All rights reserved.
+ *
+ * Derived from Intel e1000 driver
+ * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59
+ * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef ATLX_H
+#define ATLX_H
+
+#include <linux/module.h>
+#include <linux/types.h>
+
+#define ATLX_DRIVER_VERSION "2.1.1"
+MODULE_AUTHOR("Xiong Huang <xiong.huang@atheros.com>, \
+ Chris Snook <csnook@redhat.com>, Jay Cliburn <jcliburn@gmail.com>");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(ATLX_DRIVER_VERSION);
+
+#define ATLX_ERR_PHY 2
+#define ATLX_ERR_PHY_SPEED 7
+#define ATLX_ERR_PHY_RES 8
+
+#define SPEED_0 0xffff
+#define SPEED_10 10
+#define SPEED_100 100
+#define SPEED_1000 1000
+#define HALF_DUPLEX 1
+#define FULL_DUPLEX 2
+
+#define MEDIA_TYPE_AUTO_SENSOR 0
+
+/* register definitions */
+#define REG_PM_CTRLSTAT 0x44
+
+#define REG_PCIE_CAP_LIST 0x58
+
+#define REG_VPD_CAP 0x6C
+#define VPD_CAP_ID_MASK 0xFF
+#define VPD_CAP_ID_SHIFT 0
+#define VPD_CAP_NEXT_PTR_MASK 0xFF
+#define VPD_CAP_NEXT_PTR_SHIFT 8
+#define VPD_CAP_VPD_ADDR_MASK 0x7FFF
+#define VPD_CAP_VPD_ADDR_SHIFT 16
+#define VPD_CAP_VPD_FLAG 0x80000000
+
+#define REG_VPD_DATA 0x70
+
+#define REG_SPI_FLASH_CTRL 0x200
+#define SPI_FLASH_CTRL_STS_NON_RDY 0x1
+#define SPI_FLASH_CTRL_STS_WEN 0x2
+#define SPI_FLASH_CTRL_STS_WPEN 0x80
+#define SPI_FLASH_CTRL_DEV_STS_MASK 0xFF
+#define SPI_FLASH_CTRL_DEV_STS_SHIFT 0
+#define SPI_FLASH_CTRL_INS_MASK 0x7
+#define SPI_FLASH_CTRL_INS_SHIFT 8
+#define SPI_FLASH_CTRL_START 0x800
+#define SPI_FLASH_CTRL_EN_VPD 0x2000
+#define SPI_FLASH_CTRL_LDSTART 0x8000
+#define SPI_FLASH_CTRL_CS_HI_MASK 0x3
+#define SPI_FLASH_CTRL_CS_HI_SHIFT 16
+#define SPI_FLASH_CTRL_CS_HOLD_MASK 0x3
+#define SPI_FLASH_CTRL_CS_HOLD_SHIFT 18
+#define SPI_FLASH_CTRL_CLK_LO_MASK 0x3
+#define SPI_FLASH_CTRL_CLK_LO_SHIFT 20
+#define SPI_FLASH_CTRL_CLK_HI_MASK 0x3
+#define SPI_FLASH_CTRL_CLK_HI_SHIFT 22
+#define SPI_FLASH_CTRL_CS_SETUP_MASK 0x3
+#define SPI_FLASH_CTRL_CS_SETUP_SHIFT 24
+#define SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3
+#define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26
+#define SPI_FLASH_CTRL_WAIT_READY 0x10000000
+
+#define REG_SPI_ADDR 0x204
+
+#define REG_SPI_DATA 0x208
+
+#define REG_SPI_FLASH_CONFIG 0x20C
+#define SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF
+#define SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0
+#define SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3
+#define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24
+#define SPI_FLASH_CONFIG_LD_EXIST 0x4000000
+
+#define REG_SPI_FLASH_OP_PROGRAM 0x210
+#define REG_SPI_FLASH_OP_SC_ERASE 0x211
+#define REG_SPI_FLASH_OP_CHIP_ERASE 0x212
+#define REG_SPI_FLASH_OP_RDID 0x213
+#define REG_SPI_FLASH_OP_WREN 0x214
+#define REG_SPI_FLASH_OP_RDSR 0x215
+#define REG_SPI_FLASH_OP_WRSR 0x216
+#define REG_SPI_FLASH_OP_READ 0x217
+
+#define REG_TWSI_CTRL 0x218
+#define TWSI_CTRL_LD_OFFSET_MASK 0xFF
+#define TWSI_CTRL_LD_OFFSET_SHIFT 0
+#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7
+#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8
+#define TWSI_CTRL_SW_LDSTART 0x800
+#define TWSI_CTRL_HW_LDSTART 0x1000
+#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x7F
+#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15
+#define TWSI_CTRL_LD_EXIST 0x400000
+#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3
+#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23
+#define TWSI_CTRL_FREQ_SEL_100K 0
+#define TWSI_CTRL_FREQ_SEL_200K 1
+#define TWSI_CTRL_FREQ_SEL_300K 2
+#define TWSI_CTRL_FREQ_SEL_400K 3
+#define TWSI_CTRL_SMB_SLV_ADDR /* FIXME: define or remove */
+#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3
+#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24
+
+#define REG_PCIE_DEV_MISC_CTRL 0x21C
+#define PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2
+#define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1
+#define PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4
+#define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8
+#define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10
+
+#define REG_PCIE_PHYMISC 0x1000
+#define PCIE_PHYMISC_FORCE_RCV_DET 0x4
+
+#define REG_PCIE_DLL_TX_CTRL1 0x1104
+#define PCIE_DLL_TX_CTRL1_SEL_NOR_CLK 0x400
+#define PCIE_DLL_TX_CTRL1_DEF 0x568
+
+#define REG_LTSSM_TEST_MODE 0x12FC
+#define LTSSM_TEST_MODE_DEF 0x6500
+
+/* Master Control Register */
+#define REG_MASTER_CTRL 0x1400
+#define MASTER_CTRL_SOFT_RST 0x1
+#define MASTER_CTRL_MTIMER_EN 0x2
+#define MASTER_CTRL_ITIMER_EN 0x4
+#define MASTER_CTRL_MANUAL_INT 0x8
+#define MASTER_CTRL_REV_NUM_SHIFT 16
+#define MASTER_CTRL_REV_NUM_MASK 0xFF
+#define MASTER_CTRL_DEV_ID_SHIFT 24
+#define MASTER_CTRL_DEV_ID_MASK 0xFF
+
+/* Timer Initial Value Register */
+#define REG_MANUAL_TIMER_INIT 0x1404
+
+/* IRQ Moderator Timer Initial Value Register */
+#define REG_IRQ_MODU_TIMER_INIT 0x1408
+
+#define REG_PHY_ENABLE 0x140C
+
+/* IRQ Anti-Lost Timer Initial Value Register */
+#define REG_CMBDISDMA_TIMER 0x140E
+
+/* Block IDLE Status Register */
+#define REG_IDLE_STATUS 0x1410
+
+/* MDIO Control Register */
+#define REG_MDIO_CTRL 0x1414
+#define MDIO_DATA_MASK 0xFFFF
+#define MDIO_DATA_SHIFT 0
+#define MDIO_REG_ADDR_MASK 0x1F
+#define MDIO_REG_ADDR_SHIFT 16
+#define MDIO_RW 0x200000
+#define MDIO_SUP_PREAMBLE 0x400000
+#define MDIO_START 0x800000
+#define MDIO_CLK_SEL_SHIFT 24
+#define MDIO_CLK_25_4 0
+#define MDIO_CLK_25_6 2
+#define MDIO_CLK_25_8 3
+#define MDIO_CLK_25_10 4
+#define MDIO_CLK_25_14 5
+#define MDIO_CLK_25_20 6
+#define MDIO_CLK_25_28 7
+#define MDIO_BUSY 0x8000000
+
+/* MII PHY Status Register */
+#define REG_PHY_STATUS 0x1418
+
+/* BIST Control and Status Register0 (for the Packet Memory) */
+#define REG_BIST0_CTRL 0x141C
+#define BIST0_NOW 0x1
+#define BIST0_SRAM_FAIL 0x2
+#define BIST0_FUSE_FLAG 0x4
+#define REG_BIST1_CTRL 0x1420
+#define BIST1_NOW 0x1
+#define BIST1_SRAM_FAIL 0x2
+#define BIST1_FUSE_FLAG 0x4
+
+/* SerDes Lock Detect Control and Status Register */
+#define REG_SERDES_LOCK 0x1424
+#define SERDES_LOCK_DETECT 1
+#define SERDES_LOCK_DETECT_EN 2
+
+/* MAC Control Register */
+#define REG_MAC_CTRL 0x1480
+#define MAC_CTRL_TX_EN 1
+#define MAC_CTRL_RX_EN 2
+#define MAC_CTRL_TX_FLOW 4
+#define MAC_CTRL_RX_FLOW 8
+#define MAC_CTRL_LOOPBACK 0x10
+#define MAC_CTRL_DUPLX 0x20
+#define MAC_CTRL_ADD_CRC 0x40
+#define MAC_CTRL_PAD 0x80
+#define MAC_CTRL_LENCHK 0x100
+#define MAC_CTRL_HUGE_EN 0x200
+#define MAC_CTRL_PRMLEN_SHIFT 10
+#define MAC_CTRL_PRMLEN_MASK 0xF
+#define MAC_CTRL_RMV_VLAN 0x4000
+#define MAC_CTRL_PROMIS_EN 0x8000
+#define MAC_CTRL_MC_ALL_EN 0x2000000
+#define MAC_CTRL_BC_EN 0x4000000
+
+/* MAC IPG/IFG Control Register */
+#define REG_MAC_IPG_IFG 0x1484
+#define MAC_IPG_IFG_IPGT_SHIFT 0
+#define MAC_IPG_IFG_IPGT_MASK 0x7F
+#define MAC_IPG_IFG_MIFG_SHIFT 8
+#define MAC_IPG_IFG_MIFG_MASK 0xFF
+#define MAC_IPG_IFG_IPGR1_SHIFT 16
+#define MAC_IPG_IFG_IPGR1_MASK 0x7F
+#define MAC_IPG_IFG_IPGR2_SHIFT 24
+#define MAC_IPG_IFG_IPGR2_MASK 0x7F
+
+/* MAC STATION ADDRESS */
+#define REG_MAC_STA_ADDR 0x1488
+
+/* Hash table for multicast address */
+#define REG_RX_HASH_TABLE 0x1490
+
+/* MAC Half-Duplex Control Register */
+#define REG_MAC_HALF_DUPLX_CTRL 0x1498
+#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0
+#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3FF
+#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12
+#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xF
+#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000
+#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000
+#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000
+#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000
+#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20
+#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xF
+#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24
+#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xF
+
+/* Maximum Frame Length Control Register */
+#define REG_MTU 0x149C
+
+/* Wake-On-Lan control register */
+#define REG_WOL_CTRL 0x14A0
+#define WOL_PATTERN_EN 0x1
+#define WOL_PATTERN_PME_EN 0x2
+#define WOL_MAGIC_EN 0x4
+#define WOL_MAGIC_PME_EN 0x8
+#define WOL_LINK_CHG_EN 0x10
+#define WOL_LINK_CHG_PME_EN 0x20
+#define WOL_PATTERN_ST 0x100
+#define WOL_MAGIC_ST 0x200
+#define WOL_LINKCHG_ST 0x400
+#define WOL_PT0_EN 0x10000
+#define WOL_PT1_EN 0x20000
+#define WOL_PT2_EN 0x40000
+#define WOL_PT3_EN 0x80000
+#define WOL_PT4_EN 0x100000
+#define WOL_PT0_MATCH 0x1000000
+#define WOL_PT1_MATCH 0x2000000
+#define WOL_PT2_MATCH 0x4000000
+#define WOL_PT3_MATCH 0x8000000
+#define WOL_PT4_MATCH 0x10000000
+
+/* Internal SRAM Partition Register, high 32 bits */
+#define REG_SRAM_RFD_ADDR 0x1500
+
+/* Descriptor Control register, high 32 bits */
+#define REG_DESC_BASE_ADDR_HI 0x1540
+
+/* Interrupt Status Register */
+#define REG_ISR 0x1600
+#define ISR_UR_DETECTED 0x1000000
+#define ISR_FERR_DETECTED 0x2000000
+#define ISR_NFERR_DETECTED 0x4000000
+#define ISR_CERR_DETECTED 0x8000000
+#define ISR_PHY_LINKDOWN 0x10000000
+#define ISR_DIS_INT 0x80000000
+
+/* Interrupt Mask Register */
+#define REG_IMR 0x1604
+
+#define REG_RFD_RRD_IDX 0x1800
+#define REG_TPD_IDX 0x1804
+
+/* MII definitions */
+
+/* PHY Common Register */
+#define MII_ATLX_CR 0x09
+#define MII_ATLX_SR 0x0A
+#define MII_ATLX_ESR 0x0F
+#define MII_ATLX_PSCR 0x10
+#define MII_ATLX_PSSR 0x11
+
+/* PHY Control Register */
+#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100,
+ * 00=10
+ */
+#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
+#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
+#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
+#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
+#define MII_CR_POWER_DOWN 0x0800 /* Power down */
+#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
+#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100,
+ * 00=10
+ */
+#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
+#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
+#define MII_CR_SPEED_MASK 0x2040
+#define MII_CR_SPEED_1000 0x0040
+#define MII_CR_SPEED_100 0x2000
+#define MII_CR_SPEED_10 0x0000
+
+/* PHY Status Register */
+#define MII_SR_EXTENDED_CAPS 0x0001 /* Ext register capabilities */
+#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
+#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
+#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
+#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
+#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
+#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
+#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext stat info in Reg 0x0F */
+#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
+#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
+#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
+#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
+#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
+#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
+#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
+
+/* Link partner ability register */
+#define MII_LPA_SLCT 0x001f /* Same as advertise selector */
+#define MII_LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
+#define MII_LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
+#define MII_LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
+#define MII_LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
+#define MII_LPA_100BASE4 0x0200 /* 100BASE-T4 */
+#define MII_LPA_PAUSE 0x0400 /* PAUSE */
+#define MII_LPA_ASYPAUSE 0x0800 /* Asymmetrical PAUSE */
+#define MII_LPA_RFAULT 0x2000 /* Link partner faulted */
+#define MII_LPA_LPACK 0x4000 /* Link partner acked us */
+#define MII_LPA_NPAGE 0x8000 /* Next page bit */
+
+/* Autoneg Advertisement Register */
+#define MII_AR_SELECTOR_FIELD 0x0001 /* IEEE 802.3 CSMA/CD */
+#define MII_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
+#define MII_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
+#define MII_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
+#define MII_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
+#define MII_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
+#define MII_AR_PAUSE 0x0400 /* Pause operation desired */
+#define MII_AR_ASM_DIR 0x0800 /* Asymmetric Pause Dir bit */
+#define MII_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
+#define MII_AR_NEXT_PAGE 0x8000 /* Next Page ability support */
+#define MII_AR_SPEED_MASK 0x01E0
+#define MII_AR_DEFAULT_CAP_MASK 0x0DE0
+
+/* 1000BASE-T Control Register */
+#define MII_ATLX_CR_1000T_HD_CAPS 0x0100 /* Adv 1000T HD cap */
+#define MII_ATLX_CR_1000T_FD_CAPS 0x0200 /* Adv 1000T FD cap */
+#define MII_ATLX_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device,
+ * 0=DTE device */
+#define MII_ATLX_CR_1000T_MS_VALUE 0x0800 /* 1=Config PHY as Master,
+ * 0=Configure PHY as Slave */
+#define MII_ATLX_CR_1000T_MS_ENABLE 0x1000 /* 1=Man Master/Slave config,
+ * 0=Auto Master/Slave config
+ */
+#define MII_ATLX_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
+#define MII_ATLX_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
+#define MII_ATLX_CR_1000T_TEST_MODE_2 0x4000 /* Master Xmit Jitter test */
+#define MII_ATLX_CR_1000T_TEST_MODE_3 0x6000 /* Slave Xmit Jitter test */
+#define MII_ATLX_CR_1000T_TEST_MODE_4 0x8000 /* Xmitter Distortion test */
+#define MII_ATLX_CR_1000T_SPEED_MASK 0x0300
+#define MII_ATLX_CR_1000T_DEFAULT_CAP_MASK 0x0300
+
+/* 1000BASE-T Status Register */
+#define MII_ATLX_SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
+#define MII_ATLX_SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
+#define MII_ATLX_SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
+#define MII_ATLX_SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
+#define MII_ATLX_SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master
+ * 0=Slave
+ */
+#define MII_ATLX_SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config
+ * fault */
+#define MII_ATLX_SR_1000T_REMOTE_RX_STATUS_SHIFT 12
+#define MII_ATLX_SR_1000T_LOCAL_RX_STATUS_SHIFT 13
+
+/* Extended Status Register */
+#define MII_ATLX_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
+#define MII_ATLX_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
+#define MII_ATLX_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
+#define MII_ATLX_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
+
+/* ATLX PHY Specific Control Register */
+#define MII_ATLX_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Func disabled */
+#define MII_ATLX_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enbld */
+#define MII_ATLX_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
+#define MII_ATLX_PSCR_MAC_POWERDOWN 0x0008
+#define MII_ATLX_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low
+ * 0=CLK125 toggling
+ */
+#define MII_ATLX_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5,
+ * Manual MDI configuration
+ */
+#define MII_ATLX_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
+#define MII_ATLX_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover
+ * 100BASE-TX/10BASE-T: MDI
+ * Mode */
+#define MII_ATLX_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
+ * all speeds.
+ */
+#define MII_ATLX_PSCR_10BT_EXT_DIST_ENABLE 0x0080 /* 1=Enable Extended
+ * 10BASE-T distance
+ * (Lower 10BASE-T RX
+ * Threshold)
+ * 0=Normal 10BASE-T RX
+ * Threshold
+ */
+#define MII_ATLX_PSCR_MII_5BIT_ENABLE 0x0100 /* 1=5-Bit interface in
+ * 100BASE-TX
+ * 0=MII interface in
+ * 100BASE-TX
+ */
+#define MII_ATLX_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler dsbl */
+#define MII_ATLX_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
+#define MII_ATLX_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
+#define MII_ATLX_PSCR_POLARITY_REVERSAL_SHIFT 1
+#define MII_ATLX_PSCR_AUTO_X_MODE_SHIFT 5
+#define MII_ATLX_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
+
+/* ATLX PHY Specific Status Register */
+#define MII_ATLX_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
+#define MII_ATLX_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
+#define MII_ATLX_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
+#define MII_ATLX_PSSR_10MBS 0x0000 /* 00=10Mbs */
+#define MII_ATLX_PSSR_100MBS 0x4000 /* 01=100Mbs */
+#define MII_ATLX_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
+
+/* PCI Command Register Bit Definitions */
+#define PCI_REG_COMMAND 0x04 /* PCI Command Register */
+#define CMD_IO_SPACE 0x0001
+#define CMD_MEMORY_SPACE 0x0002
+#define CMD_BUS_MASTER 0x0004
+
+/* Wake Up Filter Control */
+#define ATLX_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
+#define ATLX_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
+#define ATLX_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
+#define ATLX_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */
+#define ATLX_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
+
+#define ADVERTISE_10_HALF 0x0001
+#define ADVERTISE_10_FULL 0x0002
+#define ADVERTISE_100_HALF 0x0004
+#define ADVERTISE_100_FULL 0x0008
+#define ADVERTISE_1000_HALF 0x0010
+#define ADVERTISE_1000_FULL 0x0020
+#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds */
+#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds */
+
+#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
+#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
+
+/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA */
+#define EEPROM_SUM 0xBABA
+#define NODE_ADDRESS_SIZE 6
+
+struct atlx_spi_flash_dev {
+ const char *manu_name; /* manufacturer id */
+ /* op-code */
+ u8 cmd_wrsr;
+ u8 cmd_read;
+ u8 cmd_program;
+ u8 cmd_wren;
+ u8 cmd_wrdi;
+ u8 cmd_rdsr;
+ u8 cmd_rdid;
+ u8 cmd_sector_erase;
+ u8 cmd_chip_erase;
+};
+
+#endif /* ATLX_H */
--
1.5.3.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 03/26] atl1: fix broken TSO
2008-01-01 2:22 [PATCH 00/26] atl1: divide and modernize Jay Cliburn
2008-01-01 2:22 ` [PATCH 01/26] atl1: relocate atl1 driver to /drivers/net/atlx Jay Cliburn
2008-01-01 2:22 ` [PATCH 02/26] atl1: move common functions to atlx files Jay Cliburn
@ 2008-01-01 2:22 ` Jay Cliburn
2008-01-01 2:22 ` [PATCH 04/26] atl1: add ethtool register dump Jay Cliburn
` (23 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Jay Cliburn @ 2008-01-01 2:22 UTC (permalink / raw)
To: netdev; +Cc: Jay Cliburn
The L1 tx packet descriptor expects TCP Header Length to be expressed as a
number of 32-bit dwords. The atl1 driver uses tcp_hdrlen() to populate the
field, but tcp_hdrlen() returns the header length in bytes, not in dwords.
Add a shift to convert tcp_hdrlen() to dwords when we write it to the tpd.
Also, some of our bit assignments are made to the wrong tpd words. Change
those to the correct words.
Finally, since all this fixes TSO, enable TSO by default.
Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net>
---
drivers/net/atlx/atl1.c | 29 +++++++++++------------------
1 files changed, 11 insertions(+), 18 deletions(-)
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index 0df3f32..4e98c16 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -36,7 +36,6 @@
* A very incomplete list of things that need to be dealt with:
*
* TODO:
- * Fix TSO; tx performance is horrible with TSO enabled.
* Wake on LAN.
* Add more ethtool functions.
* Fix abstruse irq enable/disable condition described here:
@@ -1308,8 +1307,8 @@ static int atl1_tso(struct atl1_adapter *adapter, struct sk_buff *skb,
tso->tsopl |= 1 << TSO_PARAM_ETHTYPE_SHIFT;
tso->tsopl |= (iph->ihl &
- CSUM_PARAM_IPHL_MASK) << CSUM_PARAM_IPHL_SHIFT;
- tso->tsopl |= (tcp_hdrlen(skb) &
+ TSO_PARAM_IPHL_MASK) << TSO_PARAM_IPHL_SHIFT;
+ tso->tsopl |= ((tcp_hdrlen(skb) >> 2) &
TSO_PARAM_TCPHDRLEN_MASK) <<
TSO_PARAM_TCPHDRLEN_SHIFT;
tso->tsopl |= (skb_shinfo(skb)->gso_size &
@@ -1472,8 +1471,8 @@ static void atl1_tx_queue(struct atl1_adapter *adapter, int count,
tpd->desc.tso.tsopl = descr->tso.tsopl;
tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
tpd->desc.data = descr->data;
- tpd->desc.csum.csumpu |= (cpu_to_le16(buffer_info->length) &
- CSUM_PARAM_BUFLEN_MASK) << CSUM_PARAM_BUFLEN_SHIFT;
+ tpd->desc.tso.tsopu |= (cpu_to_le16(buffer_info->length) &
+ TSO_PARAM_BUFLEN_MASK) << TSO_PARAM_BUFLEN_SHIFT;
val = (descr->tso.tsopl >> TSO_PARAM_SEGMENT_SHIFT) &
TSO_PARAM_SEGMENT_MASK;
@@ -1481,7 +1480,7 @@ static void atl1_tx_queue(struct atl1_adapter *adapter, int count,
tpd->desc.tso.tsopl |= 1 << TSO_PARAM_HDRFLAG_SHIFT;
if (j == (count - 1))
- tpd->desc.csum.csumpl |= 1 << CSUM_PARAM_EOP_SHIFT;
+ tpd->desc.tso.tsopl |= 1 << TSO_PARAM_EOP_SHIFT;
if (++tpd_next_to_use == tpd_ring->count)
tpd_next_to_use = 0;
@@ -1574,9 +1573,9 @@ static int atl1_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
vlan_tag = vlan_tx_tag_get(skb);
vlan_tag = (vlan_tag << 4) | (vlan_tag >> 13) |
((vlan_tag >> 9) & 0x8);
- param.csum.csumpl |= 1 << CSUM_PARAM_INSVLAG_SHIFT;
- param.csum.csumpu |= (vlan_tag & CSUM_PARAM_VALANTAG_MASK) <<
- CSUM_PARAM_VALAN_SHIFT;
+ param.tso.tsopl |= 1 << TSO_PARAM_INSVLAG_SHIFT;
+ param.tso.tsopu |= (vlan_tag & TSO_PARAM_VLANTAG_MASK) <<
+ TSO_PARAM_VLAN_SHIFT;
}
tso = atl1_tso(adapter, skb, ¶m.tso);
@@ -1595,8 +1594,8 @@ static int atl1_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
}
}
- val = (param.csum.csumpl >> CSUM_PARAM_SEGMENT_SHIFT) &
- CSUM_PARAM_SEGMENT_MASK;
+ val = (param.tso.tsopl >> TSO_PARAM_SEGMENT_SHIFT) &
+ TSO_PARAM_SEGMENT_MASK;
atl1_tx_map(adapter, skb, 1 == val);
atl1_tx_queue(adapter, count, ¶m);
netdev->trans_start = jiffies;
@@ -2091,13 +2090,7 @@ static int __devinit atl1_probe(struct pci_dev *pdev,
netdev->features = NETIF_F_HW_CSUM;
netdev->features |= NETIF_F_SG;
netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
-
- /*
- * FIXME - Until tso performance gets fixed, disable the feature.
- * Enable it with ethtool -K if desired.
- */
- /* netdev->features |= NETIF_F_TSO; */
-
+ netdev->features |= NETIF_F_TSO;
netdev->features |= NETIF_F_LLTX;
/*
--
1.5.3.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 04/26] atl1: add ethtool register dump
2008-01-01 2:22 [PATCH 00/26] atl1: divide and modernize Jay Cliburn
` (2 preceding siblings ...)
2008-01-01 2:22 ` [PATCH 03/26] atl1: fix broken TSO Jay Cliburn
@ 2008-01-01 2:22 ` Jay Cliburn
2008-01-01 2:22 ` [PATCH 05/26] atl1: print debug info if rrd error Jay Cliburn
` (22 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Jay Cliburn @ 2008-01-01 2:22 UTC (permalink / raw)
To: netdev; +Cc: Jay Cliburn
Add the ethtool register dump option to the atl1 driver.
Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net>
---
drivers/net/atlx/atl1.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++
drivers/net/atlx/atl1.h | 1 +
2 files changed, 54 insertions(+), 0 deletions(-)
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index 4e98c16..239641f 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -2513,6 +2513,57 @@ static int atl1_set_wol(struct net_device *netdev,
return 0;
}
+static int atl1_get_regs_len(struct net_device *netdev)
+{
+ return ATL1_REG_COUNT * sizeof(u32);
+}
+
+static void atl1_get_regs(struct net_device *netdev, struct ethtool_regs *regs,
+ void *p)
+{
+ struct atl1_adapter *adapter = netdev_priv(netdev);
+ struct atl1_hw *hw = &adapter->hw;
+ unsigned int i;
+ u32 *regbuf = p;
+
+ for (i = 0; i < ATL1_REG_COUNT; i++) {
+ /*
+ * This switch statement avoids reserved regions
+ * of register space.
+ */
+ switch (i) {
+ case 6 ... 9:
+ case 14:
+ case 29 ... 31:
+ case 34 ... 63:
+ case 75 ... 127:
+ case 136 ... 1023:
+ case 1027 ... 1087:
+ case 1091 ... 1151:
+ case 1194 ... 1195:
+ case 1200 ... 1201:
+ case 1206 ... 1213:
+ case 1216 ... 1279:
+ case 1290 ... 1311:
+ case 1323 ... 1343:
+ case 1358 ... 1359:
+ case 1368 ... 1375:
+ case 1378 ... 1383:
+ case 1388 ... 1391:
+ case 1393 ... 1395:
+ case 1402 ... 1403:
+ case 1410 ... 1471:
+ case 1522 ... 1535:
+ /* reserved region; don't read it */
+ regbuf[i] = 0;
+ break;
+ default:
+ /* unreserved region */
+ regbuf[i] = ioread32(hw->hw_addr + (i * sizeof(u32)));
+ }
+ }
+}
+
static void atl1_get_ringparam(struct net_device *netdev,
struct ethtool_ringparam *ring)
{
@@ -2703,6 +2754,8 @@ const struct ethtool_ops atl1_ethtool_ops = {
.get_drvinfo = atl1_get_drvinfo,
.get_wol = atl1_get_wol,
.set_wol = atl1_set_wol,
+ .get_regs_len = atl1_get_regs_len,
+ .get_regs = atl1_get_regs,
.get_ringparam = atl1_get_ringparam,
.set_ringparam = atl1_set_ringparam,
.get_pauseparam = atl1_get_pauseparam,
diff --git a/drivers/net/atlx/atl1.h b/drivers/net/atlx/atl1.h
index 538948d..30c5a8d 100644
--- a/drivers/net/atlx/atl1.h
+++ b/drivers/net/atlx/atl1.h
@@ -584,6 +584,7 @@ enum atl1_dma_req_block {
#define ATL1_DEFAULT_RFD 512
#define ATL1_MIN_RFD 128
#define ATL1_MAX_RFD 2048
+#define ATL1_REG_COUNT 1538
#define ATL1_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i]))
#define ATL1_RFD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_free_desc)
--
1.5.3.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 05/26] atl1: print debug info if rrd error
2008-01-01 2:22 [PATCH 00/26] atl1: divide and modernize Jay Cliburn
` (3 preceding siblings ...)
2008-01-01 2:22 ` [PATCH 04/26] atl1: add ethtool register dump Jay Cliburn
@ 2008-01-01 2:22 ` Jay Cliburn
2008-01-01 2:22 ` [PATCH 06/26] atl1: update initialization parameters Jay Cliburn
` (21 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Jay Cliburn @ 2008-01-01 2:22 UTC (permalink / raw)
To: netdev; +Cc: Jay Cliburn
Add some debug dev_printks if we encounter a bad receive return descriptor.
Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net>
---
drivers/net/atlx/atl1.c | 21 ++++++++++++++++++++-
1 files changed, 20 insertions(+), 1 deletions(-)
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index 239641f..262d3ca 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -1127,7 +1127,26 @@ static void atl1_intr_rx(struct atl1_adapter *adapter)
if (likely(rrd->xsz.valid)) { /* packet valid */
chk_rrd:
/* check rrd status */
- if (likely(rrd->num_buf == 1))
+ if (rrd->num_buf != 1) {
+ dev_printk(KERN_DEBUG, &adapter->pdev->dev,
+ "rx_buf_len = %d\n",
+ adapter->rx_buffer_len);
+ dev_printk(KERN_DEBUG, &adapter->pdev->dev,
+ "RRD num_buf = %d\n",
+ rrd->num_buf);
+ dev_printk(KERN_DEBUG, &adapter->pdev->dev,
+ "RRD pkt_len = %d\n",
+ rrd->xsz.xsum_sz.pkt_size);
+ dev_printk(KERN_DEBUG, &adapter->pdev->dev,
+ "RRD pkt_flg = 0x%08X\n",
+ rrd->pkt_flg);
+ dev_printk(KERN_DEBUG, &adapter->pdev->dev,
+ "RRD err_flg = 0x%08X\n",
+ rrd->err_flg);
+ dev_printk(KERN_DEBUG, &adapter->pdev->dev,
+ "RRD vlan_tag = 0x%08X\n",
+ rrd->vlan_tag);
+ } else
goto rrd_ok;
/* rrd seems to be bad */
--
1.5.3.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 06/26] atl1: update initialization parameters
2008-01-01 2:22 [PATCH 00/26] atl1: divide and modernize Jay Cliburn
` (4 preceding siblings ...)
2008-01-01 2:22 ` [PATCH 05/26] atl1: print debug info if rrd error Jay Cliburn
@ 2008-01-01 2:22 ` Jay Cliburn
2008-01-01 2:22 ` [PATCH 07/26] atl1: clarify max rx frame size Jay Cliburn
` (20 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Jay Cliburn @ 2008-01-01 2:22 UTC (permalink / raw)
To: netdev; +Cc: Jay Cliburn
Update initialization parameters to match the current vendor driver
version 1.2.40.2.
Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net>
---
drivers/net/atlx/atl1.c | 14 +++++++-------
1 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index 262d3ca..695dcbc 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -136,20 +136,20 @@ static int __devinit atl1_sw_init(struct atl1_adapter *adapter)
hw->rfd_fetch_gap = 1;
hw->rx_jumbo_th = adapter->rx_buffer_len / 8;
hw->rx_jumbo_lkah = 1;
- hw->rrd_ret_timer = 16;
- hw->tpd_burst = 4;
+ hw->rrd_ret_timer = 4; /* 8 us */
+ hw->tpd_burst = 8;
hw->tpd_fetch_th = 16;
- hw->txf_burst = 0x100;
+ hw->txf_burst = 0x200;
hw->tx_jumbo_task_th = (hw->max_frame_size + 7) >> 3;
hw->tpd_fetch_gap = 1;
hw->rcb_value = atl1_rcb_64;
hw->dma_ord = atl1_dma_ord_enh;
- hw->dmar_block = atl1_dma_req_256;
- hw->dmaw_block = atl1_dma_req_256;
+ hw->dmar_block = atl1_dma_req_1024;
+ hw->dmaw_block = atl1_dma_req_1024;
hw->cmb_rrd = 4;
hw->cmb_tpd = 4;
- hw->cmb_rx_timer = 1; /* about 2us */
- hw->cmb_tx_timer = 1; /* about 2us */
+ hw->cmb_rx_timer = 2; /* about 4us */
+ hw->cmb_tx_timer = 256; /* about 512us */
hw->smb_timer = 100000; /* about 200ms */
spin_lock_init(&adapter->lock);
--
1.5.3.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 07/26] atl1: clarify max rx frame size
2008-01-01 2:22 [PATCH 00/26] atl1: divide and modernize Jay Cliburn
` (5 preceding siblings ...)
2008-01-01 2:22 ` [PATCH 06/26] atl1: update initialization parameters Jay Cliburn
@ 2008-01-01 2:22 ` Jay Cliburn
2008-01-01 2:22 ` [PATCH 08/26] atl1: additional DMA engine configuration Jay Cliburn
` (19 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Jay Cliburn @ 2008-01-01 2:22 UTC (permalink / raw)
To: netdev; +Cc: Jay Cliburn
When we initially set max rx frame size, we don't explicitly allow room for
the VLAN header; it's done later in a somewhat obscure fashion. Let's make
it clear from the top that we've allowed enough room for the VLAN header.
Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net>
---
drivers/net/atlx/atl1.c | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index 695dcbc..c93cf19 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -113,7 +113,7 @@ static int __devinit atl1_sw_init(struct atl1_adapter *adapter)
struct atl1_hw *hw = &adapter->hw;
struct net_device *netdev = adapter->netdev;
- hw->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
+ hw->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
hw->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
adapter->wol = 0;
@@ -744,8 +744,8 @@ static u32 atl1_configure(struct atl1_adapter *adapter)
/* set Interrupt Clear Timer */
iowrite16(adapter->ict, hw->hw_addr + REG_CMBDISDMA_TIMER);
- /* set MTU, 4 : VLAN */
- iowrite32(hw->max_frame_size + 4, hw->hw_addr + REG_MTU);
+ /* set MTU size */
+ iowrite32(hw->max_frame_size, hw->hw_addr + REG_MTU);
/* jumbo size & rrd retirement timer */
value = (((u32) hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK)
--
1.5.3.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 08/26] atl1: additional DMA engine configuration
2008-01-01 2:22 [PATCH 00/26] atl1: divide and modernize Jay Cliburn
` (6 preceding siblings ...)
2008-01-01 2:22 ` [PATCH 07/26] atl1: clarify max rx frame size Jay Cliburn
@ 2008-01-01 2:22 ` Jay Cliburn
2008-01-01 2:22 ` [PATCH 09/26] atl1: refactor tx processing Jay Cliburn
` (18 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Jay Cliburn @ 2008-01-01 2:22 UTC (permalink / raw)
To: netdev; +Cc: Jay Cliburn
Add DMA engine configuration tweaks per current vendor atl1 driver version
1.2.40.2.
Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net>
---
drivers/net/atlx/atl1.c | 10 ++++++++++
drivers/net/atlx/atlx.h | 6 ++++++
2 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index c93cf19..fb0a0af 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -666,6 +666,7 @@ static u32 atl1_configure(struct atl1_adapter *adapter)
{
struct atl1_hw *hw = &adapter->hw;
u32 value;
+ u16 x;
/* clear interrupt status */
iowrite32(0xffffffff, adapter->hw.hw_addr + REG_ISR);
@@ -797,6 +798,15 @@ static u32 atl1_configure(struct atl1_adapter *adapter)
iowrite32(value, hw->hw_addr + REG_RXQ_CTRL);
/* config DMA Engine */
+ value = ioread32(hw->hw_addr + REG_DEVICE_CTRL);
+ x = (value >> DEVICE_CTRL_MAX_PAYLOAD_SHIFT) &
+ DEVICE_CTRL_MAX_PAYLOAD_MASK;
+ if (x < hw->dmaw_block)
+ hw->dmaw_block = x;
+ x = (value >> DEVICE_CTRL_MAX_RREQ_SZ_SHIFT) &
+ DEVICE_CTRL_MAX_RREQ_SZ_MASK;
+ if (x < hw->dmar_block)
+ hw->dmar_block = x;
value = ((((u32) hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
<< DMA_CTRL_DMAR_BURST_LEN_SHIFT) |
((((u32) hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
diff --git a/drivers/net/atlx/atlx.h b/drivers/net/atlx/atlx.h
index 3be7c09..43b8531 100644
--- a/drivers/net/atlx/atlx.h
+++ b/drivers/net/atlx/atlx.h
@@ -53,6 +53,12 @@ MODULE_VERSION(ATLX_DRIVER_VERSION);
#define REG_PCIE_CAP_LIST 0x58
+#define REG_DEVICE_CTRL 0x60
+#define DEVICE_CTRL_MAX_PAYLOAD_MASK 0x7
+#define DEVICE_CTRL_MAX_PAYLOAD_SHIFT 5
+#define DEVICE_CTRL_MAX_RREQ_SZ_MASK 0x7
+#define DEVICE_CTRL_MAX_RREQ_SZ_SHIFT 12
+
#define REG_VPD_CAP 0x6C
#define VPD_CAP_ID_MASK 0xFF
#define VPD_CAP_ID_SHIFT 0
--
1.5.3.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 09/26] atl1: refactor tx processing
2008-01-01 2:22 [PATCH 00/26] atl1: divide and modernize Jay Cliburn
` (7 preceding siblings ...)
2008-01-01 2:22 ` [PATCH 08/26] atl1: additional DMA engine configuration Jay Cliburn
@ 2008-01-01 2:22 ` Jay Cliburn
2008-01-01 2:22 ` [PATCH 10/26] atl1: use csum_start Jay Cliburn
` (17 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Jay Cliburn @ 2008-01-01 2:22 UTC (permalink / raw)
To: netdev; +Cc: Jay Cliburn
Refactor tx processing to use a less convoluted tx packet descriptor and
to conform generally with the vendor's current version 1.2.40.2.
Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net>
---
drivers/net/atlx/atl1.c | 265 +++++++++++++++++++++++++----------------------
drivers/net/atlx/atl1.h | 201 +++++++++++++++++++-----------------
2 files changed, 246 insertions(+), 220 deletions(-)
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index fb0a0af..b0c3273 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -1288,8 +1288,6 @@ static void atl1_intr_tx(struct atl1_adapter *adapter)
dev_kfree_skb_irq(buffer_info->skb);
buffer_info->skb = NULL;
}
- tpd->buffer_addr = 0;
- tpd->desc.data = 0;
if (++sw_tpd_next_to_clean == tpd_ring->count)
sw_tpd_next_to_clean = 0;
@@ -1311,48 +1309,69 @@ static u16 atl1_tpd_avail(struct atl1_tpd_ring *tpd_ring)
}
static int atl1_tso(struct atl1_adapter *adapter, struct sk_buff *skb,
- struct tso_param *tso)
+ struct tx_packet_desc *ptpd)
{
- /* We enter this function holding a spinlock. */
- u8 ipofst;
+ /* spinlock held */
+ u8 hdr_len, ip_off;
+ u32 real_len;
int err;
if (skb_shinfo(skb)->gso_size) {
if (skb_header_cloned(skb)) {
err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
if (unlikely(err))
- return err;
+ return -1;
}
if (skb->protocol == ntohs(ETH_P_IP)) {
struct iphdr *iph = ip_hdr(skb);
- iph->tot_len = 0;
+ real_len = (((unsigned char *)iph - skb->data) +
+ ntohs(iph->tot_len));
+ if (real_len < skb->len)
+ pskb_trim(skb, real_len);
+ hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
+ if (skb->len == hdr_len) {
+ iph->check = 0;
+ tcp_hdr(skb)->check =
+ ~csum_tcpudp_magic(iph->saddr,
+ iph->daddr, tcp_hdrlen(skb),
+ IPPROTO_TCP, 0);
+ ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) <<
+ TPD_IPHL_SHIFT;
+ ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
+ TPD_TCPHDRLEN_MASK) <<
+ TPD_TCPHDRLEN_SHIFT;
+ ptpd->word3 |= 1 << TPD_IP_CSUM_SHIFT;
+ ptpd->word3 |= 1 << TPD_TCP_CSUM_SHIFT;
+ return 1;
+ }
+
iph->check = 0;
tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
- iph->daddr, 0, IPPROTO_TCP, 0);
- ipofst = skb_network_offset(skb);
- if (ipofst != ETH_HLEN) /* 802.3 frame */
- tso->tsopl |= 1 << TSO_PARAM_ETHTYPE_SHIFT;
-
- tso->tsopl |= (iph->ihl &
- TSO_PARAM_IPHL_MASK) << TSO_PARAM_IPHL_SHIFT;
- tso->tsopl |= ((tcp_hdrlen(skb) >> 2) &
- TSO_PARAM_TCPHDRLEN_MASK) <<
- TSO_PARAM_TCPHDRLEN_SHIFT;
- tso->tsopl |= (skb_shinfo(skb)->gso_size &
- TSO_PARAM_MSS_MASK) << TSO_PARAM_MSS_SHIFT;
- tso->tsopl |= 1 << TSO_PARAM_IPCKSUM_SHIFT;
- tso->tsopl |= 1 << TSO_PARAM_TCPCKSUM_SHIFT;
- tso->tsopl |= 1 << TSO_PARAM_SEGMENT_SHIFT;
- return true;
+ iph->daddr, 0, IPPROTO_TCP, 0);
+ ip_off = (unsigned char *)iph -
+ (unsigned char *) skb_network_header(skb);
+ if (ip_off == 8) /* 802.3-SNAP frame */
+ ptpd->word3 |= 1 << TPD_ETHTYPE_SHIFT;
+ else if (ip_off != 0)
+ return -2;
+
+ ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) <<
+ TPD_IPHL_SHIFT;
+ ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
+ TPD_TCPHDRLEN_MASK) << TPD_TCPHDRLEN_SHIFT;
+ ptpd->word3 |= (skb_shinfo(skb)->gso_size &
+ TPD_MSS_MASK) << TPD_MSS_SHIFT;
+ ptpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT;
+ return 3;
}
}
return false;
}
static int atl1_tx_csum(struct atl1_adapter *adapter, struct sk_buff *skb,
- struct csum_param *csum)
+ struct tx_packet_desc *ptpd)
{
u8 css, cso;
@@ -1364,115 +1383,116 @@ static int atl1_tx_csum(struct atl1_adapter *adapter, struct sk_buff *skb,
"payload offset not an even number\n");
return -1;
}
- csum->csumpl |= (cso & CSUM_PARAM_PLOADOFFSET_MASK) <<
- CSUM_PARAM_PLOADOFFSET_SHIFT;
- csum->csumpl |= (css & CSUM_PARAM_XSUMOFFSET_MASK) <<
- CSUM_PARAM_XSUMOFFSET_SHIFT;
- csum->csumpl |= 1 << CSUM_PARAM_CUSTOMCKSUM_SHIFT;
+ ptpd->word3 |= (cso & TPD_PLOADOFFSET_MASK) <<
+ TPD_PLOADOFFSET_SHIFT;
+ ptpd->word3 |= (css & TPD_CCSUMOFFSET_MASK) <<
+ TPD_CCSUMOFFSET_SHIFT;
+ ptpd->word3 |= 1 << TPD_CUST_CSUM_EN_SHIFT;
return true;
}
-
- return true;
+ return 0;
}
static void atl1_tx_map(struct atl1_adapter *adapter, struct sk_buff *skb,
- bool tcp_seg)
+ struct tx_packet_desc *ptpd)
{
- /* We enter this function holding a spinlock. */
+ /* spinlock held */
struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
struct atl1_buffer *buffer_info;
+ u16 buf_len = skb->len;
struct page *page;
- int first_buf_len = skb->len;
unsigned long offset;
unsigned int nr_frags;
unsigned int f;
- u16 tpd_next_to_use;
- u16 proto_hdr_len;
- u16 len12;
+ int retval;
+ u16 next_to_use;
+ u16 data_len;
+ u8 hdr_len;
- first_buf_len -= skb->data_len;
+ buf_len -= skb->data_len;
nr_frags = skb_shinfo(skb)->nr_frags;
- tpd_next_to_use = atomic_read(&tpd_ring->next_to_use);
- buffer_info = &tpd_ring->buffer_info[tpd_next_to_use];
+ next_to_use = atomic_read(&tpd_ring->next_to_use);
+ buffer_info = &tpd_ring->buffer_info[next_to_use];
if (unlikely(buffer_info->skb))
BUG();
/* put skb in last TPD */
buffer_info->skb = NULL;
- if (tcp_seg) {
- /* TSO/GSO */
- proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
- buffer_info->length = proto_hdr_len;
+ retval = (ptpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK;
+ if (retval) {
+ /* TSO */
+ hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
+ buffer_info->length = hdr_len;
page = virt_to_page(skb->data);
offset = (unsigned long)skb->data & ~PAGE_MASK;
buffer_info->dma = pci_map_page(adapter->pdev, page,
- offset, proto_hdr_len,
+ offset, hdr_len,
PCI_DMA_TODEVICE);
- if (++tpd_next_to_use == tpd_ring->count)
- tpd_next_to_use = 0;
+ if (++next_to_use == tpd_ring->count)
+ next_to_use = 0;
- if (first_buf_len > proto_hdr_len) {
- int i, m;
+ if (buf_len > hdr_len) {
+ int i, nseg;
- len12 = first_buf_len - proto_hdr_len;
- m = (len12 + ATL1_MAX_TX_BUF_LEN - 1) /
+ data_len = buf_len - hdr_len;
+ nseg = (data_len + ATL1_MAX_TX_BUF_LEN - 1) /
ATL1_MAX_TX_BUF_LEN;
- for (i = 0; i < m; i++) {
+ for (i = 0; i < nseg; i++) {
buffer_info =
- &tpd_ring->buffer_info[tpd_next_to_use];
+ &tpd_ring->buffer_info[next_to_use];
buffer_info->skb = NULL;
buffer_info->length =
(ATL1_MAX_TX_BUF_LEN >=
- len12) ? ATL1_MAX_TX_BUF_LEN : len12;
- len12 -= buffer_info->length;
+ data_len) ? ATL1_MAX_TX_BUF_LEN : data_len;
+ data_len -= buffer_info->length;
page = virt_to_page(skb->data +
- (proto_hdr_len +
- i * ATL1_MAX_TX_BUF_LEN));
+ (hdr_len + i * ATL1_MAX_TX_BUF_LEN));
offset = (unsigned long)(skb->data +
- (proto_hdr_len +
- i * ATL1_MAX_TX_BUF_LEN)) & ~PAGE_MASK;
+ (hdr_len + i * ATL1_MAX_TX_BUF_LEN)) &
+ ~PAGE_MASK;
buffer_info->dma = pci_map_page(adapter->pdev,
page, offset, buffer_info->length,
PCI_DMA_TODEVICE);
- if (++tpd_next_to_use == tpd_ring->count)
- tpd_next_to_use = 0;
+ if (++next_to_use == tpd_ring->count)
+ next_to_use = 0;
}
}
} else {
- /* not TSO/GSO */
- buffer_info->length = first_buf_len;
+ /* not TSO */
+ buffer_info->length = buf_len;
page = virt_to_page(skb->data);
offset = (unsigned long)skb->data & ~PAGE_MASK;
buffer_info->dma = pci_map_page(adapter->pdev, page,
- offset, first_buf_len, PCI_DMA_TODEVICE);
- if (++tpd_next_to_use == tpd_ring->count)
- tpd_next_to_use = 0;
+ offset, buf_len, PCI_DMA_TODEVICE);
+ if (++next_to_use == tpd_ring->count)
+ next_to_use = 0;
}
for (f = 0; f < nr_frags; f++) {
struct skb_frag_struct *frag;
- u16 lenf, i, m;
+ u16 i, nseg;
frag = &skb_shinfo(skb)->frags[f];
- lenf = frag->size;
+ buf_len = frag->size;
- m = (lenf + ATL1_MAX_TX_BUF_LEN - 1) / ATL1_MAX_TX_BUF_LEN;
- for (i = 0; i < m; i++) {
- buffer_info = &tpd_ring->buffer_info[tpd_next_to_use];
+ nseg = (buf_len + ATL1_MAX_TX_BUF_LEN - 1) /
+ ATL1_MAX_TX_BUF_LEN;
+ for (i = 0; i < nseg; i++) {
+ buffer_info = &tpd_ring->buffer_info[next_to_use];
if (unlikely(buffer_info->skb))
BUG();
buffer_info->skb = NULL;
- buffer_info->length = (lenf > ATL1_MAX_TX_BUF_LEN) ?
- ATL1_MAX_TX_BUF_LEN : lenf;
- lenf -= buffer_info->length;
+ buffer_info->length = (buf_len > ATL1_MAX_TX_BUF_LEN) ?
+ ATL1_MAX_TX_BUF_LEN : buf_len;
+ buf_len -= buffer_info->length;
buffer_info->dma = pci_map_page(adapter->pdev,
frag->page,
frag->page_offset + (i * ATL1_MAX_TX_BUF_LEN),
buffer_info->length, PCI_DMA_TODEVICE);
- if (++tpd_next_to_use == tpd_ring->count)
- tpd_next_to_use = 0;
+ if (++next_to_use == tpd_ring->count)
+ next_to_use = 0;
}
}
@@ -1480,39 +1500,44 @@ static void atl1_tx_map(struct atl1_adapter *adapter, struct sk_buff *skb,
buffer_info->skb = skb;
}
-static void atl1_tx_queue(struct atl1_adapter *adapter, int count,
- union tpd_descr *descr)
+static void atl1_tx_queue(struct atl1_adapter *adapter, u16 count,
+ struct tx_packet_desc *ptpd)
{
- /* We enter this function holding a spinlock. */
+ /* spinlock held */
struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
- int j;
- u32 val;
struct atl1_buffer *buffer_info;
struct tx_packet_desc *tpd;
- u16 tpd_next_to_use = atomic_read(&tpd_ring->next_to_use);
+ u16 j;
+ u32 val;
+ u16 next_to_use = (u16) atomic_read(&tpd_ring->next_to_use);
for (j = 0; j < count; j++) {
- buffer_info = &tpd_ring->buffer_info[tpd_next_to_use];
- tpd = ATL1_TPD_DESC(&adapter->tpd_ring, tpd_next_to_use);
- tpd->desc.csum.csumpu = descr->csum.csumpu;
- tpd->desc.csum.csumpl = descr->csum.csumpl;
- tpd->desc.tso.tsopu = descr->tso.tsopu;
- tpd->desc.tso.tsopl = descr->tso.tsopl;
+ buffer_info = &tpd_ring->buffer_info[next_to_use];
+ tpd = ATL1_TPD_DESC(&adapter->tpd_ring, next_to_use);
+ if (tpd != ptpd)
+ memcpy(tpd, ptpd, sizeof(struct tx_packet_desc));
tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
- tpd->desc.data = descr->data;
- tpd->desc.tso.tsopu |= (cpu_to_le16(buffer_info->length) &
- TSO_PARAM_BUFLEN_MASK) << TSO_PARAM_BUFLEN_SHIFT;
+ tpd->word2 = (cpu_to_le16(buffer_info->length) &
+ TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT;
- val = (descr->tso.tsopl >> TSO_PARAM_SEGMENT_SHIFT) &
- TSO_PARAM_SEGMENT_MASK;
- if (val && !j)
- tpd->desc.tso.tsopl |= 1 << TSO_PARAM_HDRFLAG_SHIFT;
+ /*
+ * if this is the first packet in a TSO chain, set
+ * TPD_HDRFLAG, otherwise, clear it.
+ */
+ val = (tpd->word3 >> TPD_SEGMENT_EN_SHIFT) &
+ TPD_SEGMENT_EN_MASK;
+ if (val) {
+ if (!j)
+ tpd->word3 |= 1 << TPD_HDRFLAG_SHIFT;
+ else
+ tpd->word3 &= ~(1 << TPD_HDRFLAG_SHIFT);
+ }
if (j == (count - 1))
- tpd->desc.tso.tsopl |= 1 << TSO_PARAM_EOP_SHIFT;
+ tpd->word3 |= 1 << TPD_EOP_SHIFT;
- if (++tpd_next_to_use == tpd_ring->count)
- tpd_next_to_use = 0;
+ if (++next_to_use == tpd_ring->count)
+ next_to_use = 0;
}
/*
* Force memory writes to complete before letting h/w
@@ -1522,18 +1547,18 @@ static void atl1_tx_queue(struct atl1_adapter *adapter, int count,
*/
wmb();
- atomic_set(&tpd_ring->next_to_use, (int)tpd_next_to_use);
+ atomic_set(&tpd_ring->next_to_use, next_to_use);
}
static int atl1_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
{
struct atl1_adapter *adapter = netdev_priv(netdev);
+ struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
int len = skb->len;
int tso;
int count = 1;
int ret_val;
- u32 val;
- union tpd_descr param;
+ struct tx_packet_desc *ptpd;
u16 frag_size;
u16 vlan_tag;
unsigned long flags;
@@ -1544,18 +1569,11 @@ static int atl1_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
len -= skb->data_len;
- if (unlikely(skb->len == 0)) {
+ if (unlikely(skb->len <= 0)) {
dev_kfree_skb_any(skb);
return NETDEV_TX_OK;
}
- param.data = 0;
- param.tso.tsopu = 0;
- param.tso.tsopl = 0;
- param.csum.csumpu = 0;
- param.csum.csumpl = 0;
-
- /* nr_frags will be nonzero if we're doing scatter/gather (SG) */
nr_frags = skb_shinfo(skb)->nr_frags;
for (f = 0; f < nr_frags; f++) {
frag_size = skb_shinfo(skb)->frags[f].size;
@@ -1564,10 +1582,9 @@ static int atl1_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
ATL1_MAX_TX_BUF_LEN;
}
- /* mss will be nonzero if we're doing segment offload (TSO/GSO) */
mss = skb_shinfo(skb)->gso_size;
if (mss) {
- if (skb->protocol == htons(ETH_P_IP)) {
+ if (skb->protocol == ntohs(ETH_P_IP)) {
proto_hdr_len = (skb_transport_offset(skb) +
tcp_hdrlen(skb));
if (unlikely(proto_hdr_len > len)) {
@@ -1596,18 +1613,20 @@ static int atl1_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
return NETDEV_TX_BUSY;
}
- param.data = 0;
+ ptpd = ATL1_TPD_DESC(tpd_ring,
+ (u16) atomic_read(&tpd_ring->next_to_use));
+ memset(ptpd, 0, sizeof(struct tx_packet_desc));
if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
vlan_tag = vlan_tx_tag_get(skb);
vlan_tag = (vlan_tag << 4) | (vlan_tag >> 13) |
((vlan_tag >> 9) & 0x8);
- param.tso.tsopl |= 1 << TSO_PARAM_INSVLAG_SHIFT;
- param.tso.tsopu |= (vlan_tag & TSO_PARAM_VLANTAG_MASK) <<
- TSO_PARAM_VLAN_SHIFT;
+ ptpd->word3 |= 1 << TPD_INS_VL_TAG_SHIFT;
+ ptpd->word3 |= (vlan_tag & TPD_VL_TAGGED_MASK) <<
+ TPD_VL_TAGGED_SHIFT;
}
- tso = atl1_tso(adapter, skb, ¶m.tso);
+ tso = atl1_tso(adapter, skb, ptpd);
if (tso < 0) {
spin_unlock_irqrestore(&adapter->lock, flags);
dev_kfree_skb_any(skb);
@@ -1615,7 +1634,7 @@ static int atl1_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
}
if (!tso) {
- ret_val = atl1_tx_csum(adapter, skb, ¶m.csum);
+ ret_val = atl1_tx_csum(adapter, skb, ptpd);
if (ret_val < 0) {
spin_unlock_irqrestore(&adapter->lock, flags);
dev_kfree_skb_any(skb);
@@ -1623,13 +1642,11 @@ static int atl1_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
}
}
- val = (param.tso.tsopl >> TSO_PARAM_SEGMENT_SHIFT) &
- TSO_PARAM_SEGMENT_MASK;
- atl1_tx_map(adapter, skb, 1 == val);
- atl1_tx_queue(adapter, count, ¶m);
- netdev->trans_start = jiffies;
- spin_unlock_irqrestore(&adapter->lock, flags);
+ atl1_tx_map(adapter, skb, ptpd);
+ atl1_tx_queue(adapter, count, ptpd);
atl1_update_mailbox(adapter);
+ spin_unlock_irqrestore(&adapter->lock, flags);
+ netdev->trans_start = jiffies;
return NETDEV_TX_OK;
}
@@ -2788,7 +2805,7 @@ const struct ethtool_ops atl1_ethtool_ops = {
.get_ringparam = atl1_get_ringparam,
.set_ringparam = atl1_set_ringparam,
.get_pauseparam = atl1_get_pauseparam,
- .set_pauseparam = atl1_set_pauseparam,
+ .set_pauseparam = atl1_set_pauseparam,
.get_rx_csum = atl1_get_rx_csum,
.set_tx_csum = ethtool_op_set_tx_hw_csum,
.get_link = ethtool_op_get_link,
diff --git a/drivers/net/atlx/atl1.h b/drivers/net/atlx/atl1.h
index 30c5a8d..f50441b 100644
--- a/drivers/net/atlx/atl1.h
+++ b/drivers/net/atlx/atl1.h
@@ -452,106 +452,115 @@ struct rx_free_desc {
/* __attribute__ ((packed)) is required */
} __attribute__ ((packed));
-/* tsopu defines */
-#define TSO_PARAM_BUFLEN_MASK 0x3FFF
-#define TSO_PARAM_BUFLEN_SHIFT 0
-#define TSO_PARAM_DMAINT_MASK 0x0001
-#define TSO_PARAM_DMAINT_SHIFT 14
-#define TSO_PARAM_PKTNT_MASK 0x0001
-#define TSO_PARAM_PKTINT_SHIFT 15
-#define TSO_PARAM_VLANTAG_MASK 0xFFFF
-#define TSO_PARAM_VLAN_SHIFT 16
-
-/* tsopl defines */
-#define TSO_PARAM_EOP_MASK 0x0001
-#define TSO_PARAM_EOP_SHIFT 0
-#define TSO_PARAM_COALESCE_MASK 0x0001
-#define TSO_PARAM_COALESCE_SHIFT 1
-#define TSO_PARAM_INSVLAG_MASK 0x0001
-#define TSO_PARAM_INSVLAG_SHIFT 2
-#define TSO_PARAM_CUSTOMCKSUM_MASK 0x0001
-#define TSO_PARAM_CUSTOMCKSUM_SHIFT 3
-#define TSO_PARAM_SEGMENT_MASK 0x0001
-#define TSO_PARAM_SEGMENT_SHIFT 4
-#define TSO_PARAM_IPCKSUM_MASK 0x0001
-#define TSO_PARAM_IPCKSUM_SHIFT 5
-#define TSO_PARAM_TCPCKSUM_MASK 0x0001
-#define TSO_PARAM_TCPCKSUM_SHIFT 6
-#define TSO_PARAM_UDPCKSUM_MASK 0x0001
-#define TSO_PARAM_UDPCKSUM_SHIFT 7
-#define TSO_PARAM_VLANTAGGED_MASK 0x0001
-#define TSO_PARAM_VLANTAGGED_SHIFT 8
-#define TSO_PARAM_ETHTYPE_MASK 0x0001
-#define TSO_PARAM_ETHTYPE_SHIFT 9
-#define TSO_PARAM_IPHL_MASK 0x000F
-#define TSO_PARAM_IPHL_SHIFT 10
-#define TSO_PARAM_TCPHDRLEN_MASK 0x000F
-#define TSO_PARAM_TCPHDRLEN_SHIFT 14
-#define TSO_PARAM_HDRFLAG_MASK 0x0001
-#define TSO_PARAM_HDRFLAG_SHIFT 18
-#define TSO_PARAM_MSS_MASK 0x1FFF
-#define TSO_PARAM_MSS_SHIFT 19
-
-/* csumpu defines */
-#define CSUM_PARAM_BUFLEN_MASK 0x3FFF
-#define CSUM_PARAM_BUFLEN_SHIFT 0
-#define CSUM_PARAM_DMAINT_MASK 0x0001
-#define CSUM_PARAM_DMAINT_SHIFT 14
-#define CSUM_PARAM_PKTINT_MASK 0x0001
-#define CSUM_PARAM_PKTINT_SHIFT 15
-#define CSUM_PARAM_VALANTAG_MASK 0xFFFF
-#define CSUM_PARAM_VALAN_SHIFT 16
-
-/* csumpl defines*/
-#define CSUM_PARAM_EOP_MASK 0x0001
-#define CSUM_PARAM_EOP_SHIFT 0
-#define CSUM_PARAM_COALESCE_MASK 0x0001
-#define CSUM_PARAM_COALESCE_SHIFT 1
-#define CSUM_PARAM_INSVLAG_MASK 0x0001
-#define CSUM_PARAM_INSVLAG_SHIFT 2
-#define CSUM_PARAM_CUSTOMCKSUM_MASK 0x0001
-#define CSUM_PARAM_CUSTOMCKSUM_SHIFT 3
-#define CSUM_PARAM_SEGMENT_MASK 0x0001
-#define CSUM_PARAM_SEGMENT_SHIFT 4
-#define CSUM_PARAM_IPCKSUM_MASK 0x0001
-#define CSUM_PARAM_IPCKSUM_SHIFT 5
-#define CSUM_PARAM_TCPCKSUM_MASK 0x0001
-#define CSUM_PARAM_TCPCKSUM_SHIFT 6
-#define CSUM_PARAM_UDPCKSUM_MASK 0x0001
-#define CSUM_PARAM_UDPCKSUM_SHIFT 7
-#define CSUM_PARAM_VLANTAGGED_MASK 0x0001
-#define CSUM_PARAM_VLANTAGGED_SHIFT 8
-#define CSUM_PARAM_ETHTYPE_MASK 0x0001
-#define CSUM_PARAM_ETHTYPE_SHIFT 9
-#define CSUM_PARAM_IPHL_MASK 0x000F
-#define CSUM_PARAM_IPHL_SHIFT 10
-#define CSUM_PARAM_PLOADOFFSET_MASK 0x00FF
-#define CSUM_PARAM_PLOADOFFSET_SHIFT 16
-#define CSUM_PARAM_XSUMOFFSET_MASK 0x00FF
-#define CSUM_PARAM_XSUMOFFSET_SHIFT 24
-
-/* TPD descriptor */
-struct tso_param {
- /* The order of these declarations is important -- don't change it */
- u32 tsopu; /* tso_param upper word */
- u32 tsopl; /* tso_param lower word */
-};
-
-struct csum_param {
- /* The order of these declarations is important -- don't change it */
- u32 csumpu; /* csum_param upper word */
- u32 csumpl; /* csum_param lower word */
-};
+/*
+ * The L1 transmit packet descriptor is comprised of four 32-bit words.
+ *
+ * 31 0
+ * +---------------------------------------+
+ * | Word 0: Buffer addr lo |
+ * +---------------------------------------+
+ * | Word 1: Buffer addr hi |
+ * +---------------------------------------+
+ * | Word 2 |
+ * +---------------------------------------+
+ * | Word 3 |
+ * +---------------------------------------+
+ *
+ * Words 0 and 1 combine to form a 64-bit buffer address.
+ *
+ * Word 2 is self explanatory in the #define block below.
+ *
+ * Word 3 has two forms, depending upon the state of bits 3 and 4.
+ * If bits 3 and 4 are both zero, then bits 14:31 are unused by the
+ * hardware. Otherwise, if either bit 3 or 4 is set, the definition
+ * of bits 14:31 vary according to the following depiction.
+ *
+ * 0 End of packet 0 End of packet
+ * 1 Coalesce 1 Coalesce
+ * 2 Insert VLAN tag 2 Insert VLAN tag
+ * 3 Custom csum enable = 0 3 Custom csum enable = 1
+ * 4 Segment enable = 1 4 Segment enable = 0
+ * 5 Generate IP checksum 5 Generate IP checksum
+ * 6 Generate TCP checksum 6 Generate TCP checksum
+ * 7 Generate UDP checksum 7 Generate UDP checksum
+ * 8 VLAN tagged 8 VLAN tagged
+ * 9 Ethernet frame type 9 Ethernet frame type
+ * 10-+ 10-+
+ * 11 | IP hdr length (10:13) 11 | IP hdr length (10:13)
+ * 12 | (num 32-bit words) 12 | (num 32-bit words)
+ * 13-+ 13-+
+ * 14-+ 14 Unused
+ * 15 | TCP hdr length (14:15) 15 Unused
+ * 16 | (num 32-bit words) 16-+
+ * 17-+ 17 |
+ * 18 Header TPD flag 18 |
+ * 19-+ 19 | Payload offset
+ * 20 | 20 | (16:23)
+ * 21 | 21 |
+ * 22 | 22 |
+ * 23 | 23-+
+ * 24 | 24-+
+ * 25 | MSS (19:31) 25 |
+ * 26 | 26 |
+ * 27 | 27 | Custom csum offset
+ * 28 | 28 | (24:31)
+ * 29 | 29 |
+ * 30 | 30 |
+ * 31-+ 31-+
+ */
-union tpd_descr {
- u64 data;
- struct csum_param csum;
- struct tso_param tso;
-};
+/* tpd word 2 */
+#define TPD_BUFLEN_MASK 0x3FFF
+#define TPD_BUFLEN_SHIFT 0
+#define TPD_DMAINT_MASK 0x0001
+#define TPD_DMAINT_SHIFT 14
+#define TPD_PKTNT_MASK 0x0001
+#define TPD_PKTINT_SHIFT 15
+#define TPD_VLANTAG_MASK 0xFFFF
+#define TPD_VLAN_SHIFT 16
+
+/* tpd word 3 bits 0:13 */
+#define TPD_EOP_MASK 0x0001
+#define TPD_EOP_SHIFT 0
+#define TPD_COALESCE_MASK 0x0001
+#define TPD_COALESCE_SHIFT 1
+#define TPD_INS_VL_TAG_MASK 0x0001
+#define TPD_INS_VL_TAG_SHIFT 2
+#define TPD_CUST_CSUM_EN_MASK 0x0001
+#define TPD_CUST_CSUM_EN_SHIFT 3
+#define TPD_SEGMENT_EN_MASK 0x0001
+#define TPD_SEGMENT_EN_SHIFT 4
+#define TPD_IP_CSUM_MASK 0x0001
+#define TPD_IP_CSUM_SHIFT 5
+#define TPD_TCP_CSUM_MASK 0x0001
+#define TPD_TCP_CSUM_SHIFT 6
+#define TPD_UDP_CSUM_MASK 0x0001
+#define TPD_UDP_CSUM_SHIFT 7
+#define TPD_VL_TAGGED_MASK 0x0001
+#define TPD_VL_TAGGED_SHIFT 8
+#define TPD_ETHTYPE_MASK 0x0001
+#define TPD_ETHTYPE_SHIFT 9
+#define TPD_IPHL_MASK 0x000F
+#define TPD_IPHL_SHIFT 10
+
+/* tpd word 3 bits 14:31 if segment enabled */
+#define TPD_TCPHDRLEN_MASK 0x000F
+#define TPD_TCPHDRLEN_SHIFT 14
+#define TPD_HDRFLAG_MASK 0x0001
+#define TPD_HDRFLAG_SHIFT 18
+#define TPD_MSS_MASK 0x1FFF
+#define TPD_MSS_SHIFT 19
+
+/* tpd word 3 bits 16:31 if custom csum enabled */
+#define TPD_PLOADOFFSET_MASK 0x00FF
+#define TPD_PLOADOFFSET_SHIFT 16
+#define TPD_CCSUMOFFSET_MASK 0x00FF
+#define TPD_CCSUMOFFSET_SHIFT 24
struct tx_packet_desc {
__le64 buffer_addr;
- union tpd_descr desc;
+ __le32 word2;
+ __le32 word3;
};
/* DMA Order Settings */
--
1.5.3.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 10/26] atl1: use csum_start
2008-01-01 2:22 [PATCH 00/26] atl1: divide and modernize Jay Cliburn
` (8 preceding siblings ...)
2008-01-01 2:22 ` [PATCH 09/26] atl1: refactor tx processing Jay Cliburn
@ 2008-01-01 2:22 ` Jay Cliburn
2008-01-01 2:22 ` [PATCH 11/26] atl1: refactor initialization and startup Jay Cliburn
` (16 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Jay Cliburn @ 2008-01-01 2:22 UTC (permalink / raw)
To: netdev; +Cc: Jay Cliburn
Use skb->csum_start for tx checksum offload preparation.
Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net>
---
drivers/net/atlx/atl1.c | 11 ++++++-----
1 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index b0c3273..31aad9f 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -1376,16 +1376,17 @@ static int atl1_tx_csum(struct atl1_adapter *adapter, struct sk_buff *skb,
u8 css, cso;
if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
- cso = skb_transport_offset(skb);
- css = cso + skb->csum_offset;
- if (unlikely(cso & 0x1)) {
+ css = (u8) (skb->csum_start - skb_headroom(skb));
+ cso = css + (u8) skb->csum_offset;
+ if (unlikely(css & 0x1)) {
+ /* L1 hardware requires an even number here */
dev_printk(KERN_DEBUG, &adapter->pdev->dev,
"payload offset not an even number\n");
return -1;
}
- ptpd->word3 |= (cso & TPD_PLOADOFFSET_MASK) <<
+ ptpd->word3 |= (css & TPD_PLOADOFFSET_MASK) <<
TPD_PLOADOFFSET_SHIFT;
- ptpd->word3 |= (css & TPD_CCSUMOFFSET_MASK) <<
+ ptpd->word3 |= (cso & TPD_CCSUMOFFSET_MASK) <<
TPD_CCSUMOFFSET_SHIFT;
ptpd->word3 |= 1 << TPD_CUST_CSUM_EN_SHIFT;
return true;
--
1.5.3.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 11/26] atl1: refactor initialization and startup
2008-01-01 2:22 [PATCH 00/26] atl1: divide and modernize Jay Cliburn
` (9 preceding siblings ...)
2008-01-01 2:22 ` [PATCH 10/26] atl1: use csum_start Jay Cliburn
@ 2008-01-01 2:22 ` Jay Cliburn
2008-01-01 2:22 ` [PATCH 12/26] atl1: refactor atl1_probe Jay Cliburn
` (15 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Jay Cliburn @ 2008-01-01 2:22 UTC (permalink / raw)
To: netdev; +Cc: Jay Cliburn
Refactor atl1 initialization and startup to conform with the current
vendor driver version 1.2.40.2.
Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net>
---
drivers/net/atlx/atl1.c | 507 ++++++++++++++++++++++++-----------------------
drivers/net/atlx/atl1.h | 10 +-
drivers/net/atlx/atlx.c | 1 +
drivers/net/atlx/atlx.h | 21 ++-
4 files changed, 284 insertions(+), 255 deletions(-)
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index 31aad9f..e96f706 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -568,39 +568,6 @@ static u32 atl1_check_link(struct atl1_adapter *adapter)
return 0;
}
-/*
- * atl1_change_mtu - Change the Maximum Transfer Unit
- * @netdev: network interface device structure
- * @new_mtu: new value for maximum frame size
- *
- * Returns 0 on success, negative on failure
- */
-static int atl1_change_mtu(struct net_device *netdev, int new_mtu)
-{
- struct atl1_adapter *adapter = netdev_priv(netdev);
- int old_mtu = netdev->mtu;
- int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
-
- if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
- (max_frame > MAX_JUMBO_FRAME_SIZE)) {
- dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
- return -EINVAL;
- }
-
- adapter->hw.max_frame_size = max_frame;
- adapter->hw.tx_jumbo_task_th = (max_frame + 7) >> 3;
- adapter->rx_buffer_len = (max_frame + 7) & ~7;
- adapter->hw.rx_jumbo_th = adapter->rx_buffer_len / 8;
-
- netdev->mtu = new_mtu;
- if ((old_mtu != new_mtu) && netif_running(netdev)) {
- atl1_down(adapter);
- atl1_up(adapter);
- }
-
- return 0;
-}
-
static void set_flow_ctrl_old(struct atl1_adapter *adapter)
{
u32 hi, lo, value;
@@ -1043,6 +1010,7 @@ static void atl1_rx_checksum(struct atl1_adapter *adapter,
static u16 atl1_alloc_rx_buffers(struct atl1_adapter *adapter)
{
struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
+ struct net_device *netdev = adapter->netdev;
struct pci_dev *pdev = adapter->pdev;
struct page *page;
unsigned long offset;
@@ -1052,7 +1020,7 @@ static u16 atl1_alloc_rx_buffers(struct atl1_adapter *adapter)
u16 rfd_next_to_use, next_next;
struct rx_free_desc *rfd_desc;
- next_next = rfd_next_to_use = atomic_read(&rfd_ring->next_to_use);
+ next_next = rfd_next_to_use = (u16) atomic_read(&rfd_ring->next_to_use);
if (++next_next == rfd_ring->count)
next_next = 0;
buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
@@ -1079,7 +1047,7 @@ static u16 atl1_alloc_rx_buffers(struct atl1_adapter *adapter)
* the 14 byte MAC header is removed
*/
skb_reserve(skb, NET_IP_ALIGN);
-
+ skb->dev = netdev;
buffer_info->alloced = 1;
buffer_info->skb = skb;
buffer_info->length = (u16) adapter->rx_buffer_len;
@@ -1767,28 +1735,6 @@ static void atl1_phy_config(unsigned long data)
spin_unlock_irqrestore(&adapter->lock, flags);
}
-/*
- * Orphaned vendor comment left intact here:
- * <vendor comment>
- * If TPD Buffer size equal to 0, PCIE DMAR_TO_INT
- * will assert. We do soft reset <0x1400=1> according
- * with the SPEC. BUT, it seemes that PCIE or DMA
- * state-machine will not be reset. DMAR_TO_INT will
- * assert again and again.
- * </vendor comment>
- */
-static void atl1_tx_timeout_task(struct work_struct *work)
-{
- struct atl1_adapter *adapter =
- container_of(work, struct atl1_adapter, tx_timeout_task);
- struct net_device *netdev = adapter->netdev;
-
- netif_device_detach(netdev);
- atl1_down(adapter);
- atl1_up(adapter);
- netif_device_attach(netdev);
-}
-
int atl1_reset(struct atl1_adapter *adapter)
{
int ret;
@@ -1798,48 +1744,40 @@ int atl1_reset(struct atl1_adapter *adapter)
return atl1_init_hw(&adapter->hw);
}
-s32 atl1_up(struct atl1_adapter *adapter)
+static s32 atl1_up(struct atl1_adapter *adapter)
{
struct net_device *netdev = adapter->netdev;
int err;
- int irq_flags = IRQF_SAMPLE_RANDOM;
+ u32 retval;
/* hardware has been reset, we need to reload some things */
+ err = atl1_init_hw(&adapter->hw);
+ if (err) {
+ err = -EIO;
+ return err;
+ }
+
atlx_set_multi(netdev);
atl1_init_ring_ptrs(adapter);
atlx_restore_vlan(adapter);
err = atl1_alloc_rx_buffers(adapter);
if (unlikely(!err))
- /* no RX BUFFER allocated */
+ /* no rx buffer allocated */
return -ENOMEM;
if (unlikely(atl1_configure(adapter))) {
err = -EIO;
- goto err_up;
- }
-
- err = pci_enable_msi(adapter->pdev);
- if (err) {
- dev_info(&adapter->pdev->dev,
- "Unable to enable MSI: %d\n", err);
- irq_flags |= IRQF_SHARED;
+ return err;
}
- err = request_irq(adapter->pdev->irq, &atl1_intr, irq_flags,
- netdev->name, netdev);
- if (unlikely(err))
- goto err_up;
-
- mod_timer(&adapter->watchdog_timer, jiffies);
+ clear_bit(__ATL1_DOWN, &adapter->flags);
+ mod_timer(&adapter->watchdog_timer, jiffies + (4 * HZ));
+ retval = ioread32(&adapter->hw + REG_MASTER_CTRL);
+ retval |= MASTER_CTRL_MANUAL_INT;
+ iowrite32(retval, &adapter->hw + REG_MASTER_CTRL);
atlx_irq_enable(adapter);
- atl1_check_link(adapter);
- return 0;
-err_up:
- pci_disable_msi(adapter->pdev);
- /* free rx_buffers */
- atl1_clean_rx_ring(adapter);
- return err;
+ return 0;
}
void atl1_down(struct atl1_adapter *adapter)
@@ -1865,36 +1803,134 @@ void atl1_down(struct atl1_adapter *adapter)
atl1_clean_rx_ring(adapter);
}
+static void atl1_tx_timeout_task(struct work_struct *work)
+{
+ struct atl1_adapter *adapter =
+ container_of(work, struct atl1_adapter, tx_timeout_task);
+ struct net_device *netdev = adapter->netdev;
+
+ netif_device_detach(netdev);
+ atl1_down(adapter);
+ atl1_up(adapter);
+ netif_device_attach(netdev);
+}
+
/*
- * atl1_open - Called when a network interface is made active
+ * atl1_change_mtu - Change the Maximum Transfer Unit
* @netdev: network interface device structure
+ * @new_mtu: new value for maximum frame size
*
- * Returns 0 on success, negative value on failure
- *
- * The open entry point is called when a network interface is made
- * active by the system (IFF_UP). At this point all resources needed
- * for transmit and receive operations are allocated, the interrupt
- * handler is registered with the OS, the watchdog timer is started,
- * and the stack is notified that the interface is ready.
+ * Returns 0 on success, negative on failure
+ */
+static int atl1_change_mtu(struct net_device *netdev, int new_mtu)
+{
+ struct atl1_adapter *adapter = netdev_priv(netdev);
+ int old_mtu = netdev->mtu;
+ int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
+
+ if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
+ (max_frame > MAX_JUMBO_FRAME_SIZE)) {
+ dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
+ return -EINVAL;
+ }
+
+ adapter->hw.max_frame_size = max_frame;
+ adapter->hw.tx_jumbo_task_th = (max_frame + 7) >> 3;
+ adapter->rx_buffer_len = (max_frame + 7) & ~7;
+ adapter->hw.rx_jumbo_th = adapter->rx_buffer_len / 8;
+
+ netdev->mtu = new_mtu;
+ if ((old_mtu != new_mtu) && netif_running(netdev)) {
+ atl1_down(adapter);
+ atl1_up(adapter);
+ }
+
+ return 0;
+}
+
+static int atl1_request_irq(struct atl1_adapter *adapter)
+{
+ struct net_device *netdev = adapter->netdev;
+ int flags, err;
+
+ flags = IRQF_SHARED;
+#ifdef CONFIG_PCI_MSI
+ adapter->have_msi = true;
+
+ err = pci_enable_msi(adapter->pdev);
+ if (err)
+ adapter->have_msi = false;
+
+ if (adapter->have_msi)
+ flags &= ~IRQF_SHARED;
+#endif
+
+ err = request_irq(adapter->pdev->irq, &atl1_intr, flags, netdev->name,
+ netdev);
+ if (err)
+ dev_printk(KERN_DEBUG, &adapter->pdev->dev,
+ "unable to obtain irq: err = %d\n", err);
+
+ return err;
+}
+
+/*
+ * atl1_open - Called when a network interface is made active
+ * @netdev: network interface device structure
*/
static int atl1_open(struct net_device *netdev)
{
struct atl1_adapter *adapter = netdev_priv(netdev);
+ struct atl1_hw *hw = &adapter->hw;
int err;
+ u32 val;
+
+ if (test_bit(__ATL1_TESTING, &adapter->flags))
+ return -EBUSY;
/* allocate transmit descriptors */
err = atl1_setup_ring_resources(adapter);
if (err)
return err;
- err = atl1_up(adapter);
+ err = atl1_init_hw(hw);
+ if (err) {
+ err = -EIO;
+ goto err_open;
+ }
+
+ atlx_set_multi(netdev);
+ atl1_init_ring_ptrs(adapter);
+ atlx_restore_vlan(adapter);
+
+ err = atl1_alloc_rx_buffers(adapter);
+ if (!err) {
+ err = -ENOMEM;
+ goto err_open;
+ }
+
+ err = atl1_configure(adapter);
+ if (err) {
+ err = -EIO;
+ goto err_open;
+ }
+
+ err = atl1_request_irq(adapter);
if (err)
- goto err_up;
+ goto err_open;
+
+ clear_bit(__ATL1_DOWN, &adapter->flags);
+ mod_timer(&adapter->watchdog_timer, jiffies + (4 * HZ));
+ val = ioread32(hw->hw_addr + REG_MASTER_CTRL);
+ val |= MASTER_CTRL_MANUAL_INT;
+ iowrite32(val, hw->hw_addr + REG_MASTER_CTRL);
+ atlx_irq_enable(adapter);
return 0;
-err_up:
- atl1_reset(adapter);
+err_open:
+ atl1_free_ring_resources(adapter);
+ atl1_reset_hw(hw);
return err;
}
@@ -1937,7 +1973,6 @@ static int atl1_suspend(struct pci_dev *pdev, pm_message_t state)
/* reduce speed to 10/100M */
if (wufc) {
- atl1_phy_enter_power_saving(hw);
/* if resume, let driver to re- setup link */
hw->phy_configured = false;
atl1_set_mac_addr(hw);
@@ -2830,15 +2865,6 @@ s32 atl1_reset_hw(struct atl1_hw *hw)
int i;
/*
- * Clear Interrupt mask to stop board from generating
- * interrupts & Clear any pending interrupt events
- */
- /*
- * iowrite32(0, hw->hw_addr + REG_IMR);
- * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
- */
-
- /*
* Issue Soft Reset to the MAC. This will reset the chip's
* transmit, receive, DMA. It will not effect
* the current PCI configuration. The global reset bit is self-
@@ -2847,20 +2873,16 @@ s32 atl1_reset_hw(struct atl1_hw *hw)
iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
ioread32(hw->hw_addr + REG_MASTER_CTRL);
- iowrite16(1, hw->hw_addr + REG_PHY_ENABLE);
- ioread16(hw->hw_addr + REG_PHY_ENABLE);
-
/* delay about 1ms */
msleep(1);
- /* Wait at least 10ms for All module to be Idle */
+ /* wait at least 10ms for idle */
for (i = 0; i < 10; i++) {
icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
if (!icr)
break;
/* delay 1 ms */
msleep(1);
- /* FIXME: still the right way to do this? */
cpu_relax();
}
@@ -2880,6 +2902,7 @@ s32 atl1_reset_hw(struct atl1_hw *hw)
static int atl1_check_eeprom_exist(struct atl1_hw *hw)
{
u32 value;
+
value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
if (value & SPI_FLASH_CTRL_EN_VPD) {
value &= ~SPI_FLASH_CTRL_EN_VPD;
@@ -3194,96 +3217,6 @@ s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
}
/*
- * Make L001's PHY out of Power Saving State (bug)
- * hw - Struct containing variables accessed by shared code
- * when power on, L001's PHY always on Power saving State
- * (Gigabit Link forbidden)
- */
-static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
-{
- s32 ret;
- ret = atl1_write_phy_reg(hw, 29, 0x0029);
- if (ret)
- return ret;
- return atl1_write_phy_reg(hw, 30, 0);
-}
-
-/*
- *TODO: do something or get rid of this
- */
-s32 atl1_phy_enter_power_saving(struct atl1_hw *hw)
-{
-/* s32 ret_val;
- * u16 phy_data;
- */
-
-/*
- ret_val = atl1_write_phy_reg(hw, ...);
- ret_val = atl1_write_phy_reg(hw, ...);
- ....
-*/
- return 0;
-}
-
-/*
- * Resets the PHY and make all config validate
- * hw - Struct containing variables accessed by shared code
- *
- * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
- */
-static s32 atl1_phy_reset(struct atl1_hw *hw)
-{
- struct pci_dev *pdev = hw->back->pdev;
- s32 ret_val;
- u16 phy_data;
-
- if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
- hw->media_type == MEDIA_TYPE_1000M_FULL)
- phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
- else {
- switch (hw->media_type) {
- case MEDIA_TYPE_100M_FULL:
- phy_data =
- MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
- MII_CR_RESET;
- break;
- case MEDIA_TYPE_100M_HALF:
- phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
- break;
- case MEDIA_TYPE_10M_FULL:
- phy_data =
- MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
- break;
- default:
- /* MEDIA_TYPE_10M_HALF: */
- phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
- break;
- }
- }
-
- ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
- if (ret_val) {
- u32 val;
- int i;
- /* pcie serdes link may be down! */
- dev_dbg(&pdev->dev, "pcie phy link down\n");
-
- for (i = 0; i < 25; i++) {
- msleep(1);
- val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
- if (!(val & (MDIO_START | MDIO_BUSY)))
- break;
- }
-
- if ((val & (MDIO_START | MDIO_BUSY)) != 0) {
- dev_warn(&pdev->dev, "pcie link down at least 25ms\n");
- return ret_val;
- }
- }
- return 0;
-}
-
-/*
* Configures PHY autoneg and flow control advertisement settings
* hw - Struct containing variables accessed by shared code
*/
@@ -3318,26 +3251,31 @@ s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
MII_AR_100TX_HD_CAPS |
MII_AR_100TX_FD_CAPS);
mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
- break;
-
- case MEDIA_TYPE_1000M_FULL:
- mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
+ hw->autoneg_advertised = ADVERTISE_10_HALF |
+ ADVERTISE_10_FULL |
+ ADVERTISE_100_HALF |
+ ADVERTISE_100_FULL |
+ ADVERTISE_1000_FULL;
break;
case MEDIA_TYPE_100M_FULL:
- mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
+ mii_1000t_ctrl_reg |= MII_AR_100TX_FD_CAPS;
+ hw->autoneg_advertised = ADVERTISE_100_FULL;
break;
case MEDIA_TYPE_100M_HALF:
mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
+ hw->autoneg_advertised = ADVERTISE_100_HALF;
break;
case MEDIA_TYPE_10M_FULL:
mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
+ hw->autoneg_advertised = ADVERTISE_10_FULL;
break;
default:
mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
+ hw->autoneg_advertised = ADVERTISE_10_HALF;
break;
}
@@ -3358,38 +3296,6 @@ s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
return 0;
}
-/*
- * Configures link settings.
- * hw - Struct containing variables accessed by shared code
- * Assumes the hardware has previously been reset and the
- * transmitter and receiver are not enabled.
- */
-static s32 atl1_setup_link(struct atl1_hw *hw)
-{
- struct pci_dev *pdev = hw->back->pdev;
- s32 ret_val;
-
- /*
- * Options:
- * PHY will advertise value(s) parsed from
- * autoneg_advertised and fc
- * no matter what autoneg is , We will not wait link result.
- */
- ret_val = atl1_phy_setup_autoneg_adv(hw);
- if (ret_val) {
- dev_dbg(&pdev->dev, "error setting up autonegotiation\n");
- return ret_val;
- }
- /* SW.Reset , En-Auto-Neg if needed */
- ret_val = atl1_phy_reset(hw);
- if (ret_val) {
- dev_dbg(&pdev->dev, "error resetting phy\n");
- return ret_val;
- }
- hw->phy_configured = true;
- return ret_val;
-}
-
static void atl1_init_flash_opcode(struct atl1_hw *hw)
{
if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
@@ -3415,6 +3321,116 @@ static void atl1_init_flash_opcode(struct atl1_hw *hw)
hw->hw_addr + REG_SPI_FLASH_OP_READ);
}
+static void atl1_init_pcie(struct atl1_hw *hw)
+{
+ u32 val;
+
+ val = LTSSM_TEST_MODE_DEF;
+ iowrite32(val, hw->hw_addr + REG_LTSSM_TEST_MODE);
+ val = ioread32(hw->hw_addr + REG_PCIE_PHY_MISC3);
+ val |= PCIE_PHY_MISC3_DS_PWR_DOWN;
+ iowrite32(val, hw->hw_addr + REG_PCIE_PHY_MISC3);
+}
+
+static bool atl1_check_cable(struct atl1_hw *hw)
+{
+ u16 pair_num;
+ u16 i;
+ u16 phy_val;
+
+ phy_val = 0x8000;
+ atl1_write_phy_reg(hw, MII_BMCR, phy_val);
+
+ for (pair_num = 0; pair_num < 4; pair_num++) {
+ phy_val = (u16) (pair_num << CDTC_PAIR_OFFSET);
+ phy_val |= CDTC_EN;
+ atl1_write_phy_reg(hw, MII_CDTC, phy_val);
+ for (i = 0; i < 200; i++) {
+ msleep(1);
+ atl1_read_phy_reg(hw, MII_CDTC, &phy_val);
+ if (!(phy_val & CDTC_EN))
+ break;
+ }
+ msleep(1);
+ atl1_read_phy_reg(hw, MII_CDTS, &phy_val);
+ if (((phy_val >> CDTS_STATUS_OFFSET) & 3) != CDTS_OPEN)
+ return true;
+ }
+ return false;
+}
+static s32 atl1_phy_commit(struct atl1_hw *hw)
+{
+ s32 retval;
+ u16 phy_data;
+ u32 val;
+ int i;
+
+ phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
+ retval = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
+ if (retval) {
+ for (i = 0; i < 25; i++) {
+ msleep(1);
+ val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
+ if (!(val & (MDIO_START | MDIO_BUSY)))
+ break;
+ }
+ if (val & (MDIO_START | MDIO_BUSY))
+ return retval;
+ }
+ return 0;
+}
+
+static s32 atl1_phy_init(struct atl1_hw *hw)
+{
+ u16 phy_data;
+ u16 i;
+ s32 retval;
+
+ if (hw->phy_configured)
+ return 0;
+
+ iowrite16(0, hw->hw_addr + REG_PHY_ENABLE);
+ msleep(2);
+ iowrite16(PHY_RESET, hw->hw_addr + REG_PHY_ENABLE);
+ msleep(2);
+
+ /* check for cable */
+ if (!atl1_check_cable(hw))
+ set_bit(0, &hw->force_ps);
+ else
+ clear_bit(0, &hw->force_ps);
+
+ /* enable PHY link change interrupt */
+ retval = atl1_write_phy_reg(hw, 18, 0xC00);
+ if (retval)
+ return retval;
+
+ /* setup autonegotiation parameters */
+ retval = atl1_phy_setup_autoneg_adv(hw);
+ if (retval)
+ return retval;
+
+ retval = atl1_phy_commit(hw);
+ if (retval)
+ return retval;
+
+ if (test_bit(0, &hw->force_ps)) {
+ atl1_write_phy_reg(hw, MII_DBG_ADDR, 0);
+ atl1_write_phy_reg(hw, MII_DBG_DATA, 0x124E);
+ atl1_write_phy_reg(hw, MII_DBG_ADDR, 1);
+ atl1_read_phy_reg(hw, MII_DBG_DATA, &phy_data);
+ phy_data |= 0x3;
+ atl1_write_phy_reg(hw, MII_DBG_DATA, phy_data);
+
+ for (i = 0; i < 15; i++)
+ msleep(100);
+ atl1_write_phy_reg(hw, MII_DBG_ADDR, 0);
+ atl1_write_phy_reg(hw, MII_DBG_DATA, 0x024E);
+ }
+ hw->phy_configured = true;
+ return retval;
+}
+
/*
* Performs basic configuration of the adapter.
* hw - Struct containing variables accessed by shared code
@@ -3425,28 +3441,15 @@ static void atl1_init_flash_opcode(struct atl1_hw *hw)
*/
s32 atl1_init_hw(struct atl1_hw *hw)
{
- u32 ret_val = 0;
+ u32 retval = 0;
- /* Zero out the Multicast HASH table */
+ atl1_init_pcie(hw);
iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
- /* clear the old settings from the multicast hash table */
iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
-
atl1_init_flash_opcode(hw);
+ retval = atl1_phy_init(hw);
- if (!hw->phy_configured) {
- /* enable GPHY LinkChange Interrrupt */
- ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
- if (ret_val)
- return ret_val;
- /* make PHY out of power-saving state */
- ret_val = atl1_phy_leave_power_saving(hw);
- if (ret_val)
- return ret_val;
- /* Call a subroutine to configure the link */
- ret_val = atl1_setup_link(hw);
- }
- return ret_val;
+ return retval;
}
/*
diff --git a/drivers/net/atlx/atl1.h b/drivers/net/atlx/atl1.h
index f50441b..c1b99f2 100644
--- a/drivers/net/atlx/atl1.h
+++ b/drivers/net/atlx/atl1.h
@@ -73,7 +73,6 @@ void atl1_check_options(struct atl1_adapter *adapter);
static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
int cmd);
static u32 atl1_check_link(struct atl1_adapter *adapter);
-s32 atl1_up(struct atl1_adapter *adapter);
void atl1_down(struct atl1_adapter *adapter);
int atl1_reset(struct atl1_adapter *adapter);
@@ -762,6 +761,7 @@ struct atl1_hw {
u8 perm_mac_addr[ETH_ALEN];
bool phy_configured;
+ unsigned long force_ps;
};
struct atl1_adapter {
@@ -801,9 +801,17 @@ struct atl1_adapter {
u32 bd_number; /* board number */
bool pci_using_64;
+ bool have_msi;
struct atl1_hw hw;
struct atl1_smb smb;
struct atl1_cmb cmb;
+ unsigned long flags;
+};
+
+enum atl1_state {
+ __ATL1_TESTING,
+ __ATL1_RESETTING,
+ __ATL1_DOWN
};
#endif /* ATL1_H */
diff --git a/drivers/net/atlx/atlx.c b/drivers/net/atlx/atlx.c
index 4186326..354050f 100644
--- a/drivers/net/atlx/atlx.c
+++ b/drivers/net/atlx/atlx.c
@@ -157,6 +157,7 @@ static void atlx_set_multi(struct net_device *netdev)
*/
static void atlx_irq_enable(struct atlx_adapter *adapter)
{
+ iowrite32(0, adapter->hw.hw_addr + REG_IMR);
iowrite32(IMR_NORMAL_MASK, adapter->hw.hw_addr + REG_IMR);
ioread32(adapter->hw.hw_addr + REG_IMR);
}
diff --git a/drivers/net/atlx/atlx.h b/drivers/net/atlx/atlx.h
index 43b8531..352432e 100644
--- a/drivers/net/atlx/atlx.h
+++ b/drivers/net/atlx/atlx.h
@@ -142,8 +142,11 @@ MODULE_VERSION(ATLX_DRIVER_VERSION);
#define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8
#define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10
-#define REG_PCIE_PHYMISC 0x1000
-#define PCIE_PHYMISC_FORCE_RCV_DET 0x4
+#define REG_PCIE_PHY_MISC1 0x1000
+#define PCIE_PHY_MISC1_FORCE_RCV_DET 0x4
+
+#define REG_PCIE_PHY_MISC3 0x1008
+#define PCIE_PHY_MISC3_DS_PWR_DOWN 0x8000
#define REG_PCIE_DLL_TX_CTRL1 0x1104
#define PCIE_DLL_TX_CTRL1_SEL_NOR_CLK 0x400
@@ -170,6 +173,7 @@ MODULE_VERSION(ATLX_DRIVER_VERSION);
#define REG_IRQ_MODU_TIMER_INIT 0x1408
#define REG_PHY_ENABLE 0x140C
+#define PHY_RESET 0x1
/* IRQ Anti-Lost Timer Initial Value Register */
#define REG_CMBDISDMA_TIMER 0x140E
@@ -319,6 +323,10 @@ MODULE_VERSION(ATLX_DRIVER_VERSION);
#define MII_ATLX_ESR 0x0F
#define MII_ATLX_PSCR 0x10
#define MII_ATLX_PSSR 0x11
+#define MII_DBG_ADDR 0x1D
+#define MII_DBG_DATA 0x1E
+#define MII_CDTC 0x16
+#define MII_CDTS 0x1C
/* PHY Control Register */
#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100,
@@ -466,6 +474,15 @@ MODULE_VERSION(ATLX_DRIVER_VERSION);
#define MII_ATLX_PSSR_100MBS 0x4000 /* 01=100Mbs */
#define MII_ATLX_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
+#define CDTC_EN 1
+#define CDTS_NORMAL 0
+#define CDTS_SHORT 1
+#define CDTS_OPEN 2
+#define CDTS_INVALID 3
+#define CDTC_PAIR_OFFSET 8
+#define CDTS_STATUS_OFFSET 8
+#define CDTS_RESULT_OFFSET 0
+
/* PCI Command Register Bit Definitions */
#define PCI_REG_COMMAND 0x04 /* PCI Command Register */
#define CMD_IO_SPACE 0x0001
--
1.5.3.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 12/26] atl1: refactor atl1_probe
2008-01-01 2:22 [PATCH 00/26] atl1: divide and modernize Jay Cliburn
` (10 preceding siblings ...)
2008-01-01 2:22 ` [PATCH 11/26] atl1: refactor initialization and startup Jay Cliburn
@ 2008-01-01 2:22 ` Jay Cliburn
2008-01-01 2:22 ` [PATCH 13/26] atl1: refactor interrupt handling Jay Cliburn
` (14 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Jay Cliburn @ 2008-01-01 2:22 UTC (permalink / raw)
To: netdev; +Cc: Jay Cliburn
Refactor atl1_probe to conform with current vendor driver version 1.2.40.2.
Also reorder functions to minimize the need for forward declarations.
Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net>
---
drivers/net/atlx/atl1.c | 1397 +++++++++++++++++++++++------------------------
drivers/net/atlx/atl1.h | 21 +-
2 files changed, 691 insertions(+), 727 deletions(-)
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index e96f706..d38f26f 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -101,17 +101,681 @@ static const struct pci_device_id atl1_pci_tbl[] = {
MODULE_DEVICE_TABLE(pci, atl1_pci_tbl);
/*
+ * Reset the transmit and receive units; mask and clear all interrupts.
+ * hw - Struct containing variables accessed by shared code
+ * return : 0 or idle status (if error)
+ */
+static s32 atl1_reset_hw(struct atl1_hw *hw)
+{
+ struct pci_dev *pdev = hw->back->pdev;
+ u32 icr;
+ int i;
+
+ /*
+ * Issue Soft Reset to the MAC. This will reset the chip's
+ * transmit, receive, DMA. It will not effect
+ * the current PCI configuration. The global reset bit is self-
+ * clearing, and should clear within a microsecond.
+ */
+ iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
+ ioread32(hw->hw_addr + REG_MASTER_CTRL);
+
+ /* delay about 1ms */
+ msleep(1);
+
+ /* wait at least 10ms for idle */
+ for (i = 0; i < 10; i++) {
+ icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
+ if (!icr)
+ break;
+ /* delay 1 ms */
+ msleep(1);
+ cpu_relax();
+ }
+
+ if (icr) {
+ dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr);
+ return icr;
+ }
+
+ return 0;
+}
+
+/* function about EEPROM
+ *
+ * check_eeprom_exist
+ * return 0 if eeprom exist
+ */
+static int atl1_check_eeprom_exist(struct atl1_hw *hw)
+{
+ u32 value;
+
+ value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
+ if (value & SPI_FLASH_CTRL_EN_VPD) {
+ value &= ~SPI_FLASH_CTRL_EN_VPD;
+ iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
+ }
+
+ value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
+ return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
+}
+
+static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
+{
+ int i;
+ u32 control;
+
+ if (offset & 3)
+ /* address do not align */
+ return false;
+
+ iowrite32(0, hw->hw_addr + REG_VPD_DATA);
+ control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
+ iowrite32(control, hw->hw_addr + REG_VPD_CAP);
+ ioread32(hw->hw_addr + REG_VPD_CAP);
+
+ for (i = 0; i < 10; i++) {
+ msleep(2);
+ control = ioread32(hw->hw_addr + REG_VPD_CAP);
+ if (control & VPD_CAP_VPD_FLAG)
+ break;
+ }
+ if (control & VPD_CAP_VPD_FLAG) {
+ *p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
+ return true;
+ }
+ /* timeout */
+ return false;
+}
+
+/*
+ * Reads the value from a PHY register
+ * hw - Struct containing variables accessed by shared code
+ * reg_addr - address of the PHY register to read
+ */
+static s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
+{
+ u32 val;
+ int i;
+
+ val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
+ MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
+ MDIO_CLK_SEL_SHIFT;
+ iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
+ ioread32(hw->hw_addr + REG_MDIO_CTRL);
+
+ for (i = 0; i < MDIO_WAIT_TIMES; i++) {
+ udelay(2);
+ val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
+ if (!(val & (MDIO_START | MDIO_BUSY)))
+ break;
+ }
+ if (!(val & (MDIO_START | MDIO_BUSY))) {
+ *phy_data = (u16) val;
+ return 0;
+ }
+ return ATLX_ERR_PHY;
+}
+
+#define CUSTOM_SPI_CS_SETUP 2
+#define CUSTOM_SPI_CLK_HI 2
+#define CUSTOM_SPI_CLK_LO 2
+#define CUSTOM_SPI_CS_HOLD 2
+#define CUSTOM_SPI_CS_HI 3
+
+static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
+{
+ int i;
+ u32 value;
+
+ iowrite32(0, hw->hw_addr + REG_SPI_DATA);
+ iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
+
+ value = SPI_FLASH_CTRL_WAIT_READY |
+ (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
+ SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
+ SPI_FLASH_CTRL_CLK_HI_MASK) <<
+ SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
+ SPI_FLASH_CTRL_CLK_LO_MASK) <<
+ SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
+ SPI_FLASH_CTRL_CS_HOLD_MASK) <<
+ SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
+ SPI_FLASH_CTRL_CS_HI_MASK) <<
+ SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
+ SPI_FLASH_CTRL_INS_SHIFT;
+
+ iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
+
+ value |= SPI_FLASH_CTRL_START;
+ iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
+ ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
+
+ for (i = 0; i < 10; i++) {
+ msleep(1);
+ value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
+ if (!(value & SPI_FLASH_CTRL_START))
+ break;
+ }
+
+ if (value & SPI_FLASH_CTRL_START)
+ return false;
+
+ *buf = ioread32(hw->hw_addr + REG_SPI_DATA);
+
+ return true;
+}
+
+/*
+ * get_permanent_address
+ * return 0 if get valid mac address,
+ */
+static int atl1_get_permanent_address(struct atl1_hw *hw)
+{
+ u32 addr[2];
+ u32 i, control;
+ u16 reg;
+ u8 eth_addr[ETH_ALEN];
+ bool key_valid;
+
+ if (is_valid_ether_addr(hw->perm_mac_addr))
+ return 0;
+
+ /* init */
+ addr[0] = addr[1] = 0;
+
+ if (!atl1_check_eeprom_exist(hw)) {
+ reg = 0;
+ key_valid = false;
+ /* Read out all EEPROM content */
+ i = 0;
+ while (1) {
+ if (atl1_read_eeprom(hw, i + 0x100, &control)) {
+ if (key_valid) {
+ if (reg == REG_MAC_STA_ADDR)
+ addr[0] = control;
+ else if (reg == (REG_MAC_STA_ADDR + 4))
+ addr[1] = control;
+ key_valid = false;
+ } else if ((control & 0xff) == 0x5A) {
+ key_valid = true;
+ reg = (u16) (control >> 16);
+ } else
+ break;
+ } else
+ /* read error */
+ break;
+ i += 4;
+ }
+
+ *(u32 *) ð_addr[2] = swab32(addr[0]);
+ *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]);
+ if (is_valid_ether_addr(eth_addr)) {
+ memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
+ return 0;
+ }
+ return 1;
+ }
+
+ /* see if SPI FLAGS exist ? */
+ addr[0] = addr[1] = 0;
+ reg = 0;
+ key_valid = false;
+ i = 0;
+ while (1) {
+ if (atl1_spi_read(hw, i + 0x1f000, &control)) {
+ if (key_valid) {
+ if (reg == REG_MAC_STA_ADDR)
+ addr[0] = control;
+ else if (reg == (REG_MAC_STA_ADDR + 4))
+ addr[1] = control;
+ key_valid = false;
+ } else if ((control & 0xff) == 0x5A) {
+ key_valid = true;
+ reg = (u16) (control >> 16);
+ } else
+ /* data end */
+ break;
+ } else
+ /* read error */
+ break;
+ i += 4;
+ }
+
+ *(u32 *) ð_addr[2] = swab32(addr[0]);
+ *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]);
+ if (is_valid_ether_addr(eth_addr)) {
+ memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
+ return 0;
+ }
+
+ /*
+ * On some motherboards, the MAC address is written by the
+ * BIOS directly to the MAC register during POST, and is
+ * not stored in eeprom. If all else thus far has failed
+ * to fetch the permanent MAC address, try reading it directly.
+ */
+ addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
+ addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
+ *(u32 *) ð_addr[2] = swab32(addr[0]);
+ *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]);
+ if (is_valid_ether_addr(eth_addr)) {
+ memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
+ return 0;
+ }
+
+ return 1;
+}
+
+/*
+ * Reads the adapter's MAC address from the EEPROM
+ * hw - Struct containing variables accessed by shared code
+ */
+static s32 atl1_read_mac_addr(struct atl1_hw *hw)
+{
+ u16 i;
+
+ if (atl1_get_permanent_address(hw))
+ random_ether_addr(hw->perm_mac_addr);
+
+ for (i = 0; i < ETH_ALEN; i++)
+ hw->mac_addr[i] = hw->perm_mac_addr[i];
+ return 0;
+}
+
+/*
+ * Hashes an address to determine its location in the multicast table
+ * hw - Struct containing variables accessed by shared code
+ * mc_addr - the multicast address to hash
+ *
+ * atl1_hash_mc_addr
+ * purpose
+ * set hash value for a multicast address
+ * hash calcu processing :
+ * 1. calcu 32bit CRC for multicast address
+ * 2. reverse crc with MSB to LSB
+ */
+static u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
+{
+ u32 crc32, value = 0;
+ int i;
+
+ crc32 = ether_crc_le(6, mc_addr);
+ for (i = 0; i < 32; i++)
+ value |= (((crc32 >> i) & 1) << (31 - i));
+
+ return value;
+}
+
+/*
+ * Sets the bit in the multicast table corresponding to the hash value.
+ * hw - Struct containing variables accessed by shared code
+ * hash_value - Multicast address hash value
+ */
+static void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
+{
+ u32 hash_bit, hash_reg;
+ u32 mta;
+
+ /*
+ * The HASH Table is a register array of 2 32-bit registers.
+ * It is treated like an array of 64 bits. We want to set
+ * bit BitArray[hash_value]. So we figure out what register
+ * the bit is in, read it, OR in the new bit, then write
+ * back the new value. The register is determined by the
+ * upper 7 bits of the hash value and the bit within that
+ * register are determined by the lower 5 bits of the value.
+ */
+ hash_reg = (hash_value >> 31) & 0x1;
+ hash_bit = (hash_value >> 26) & 0x1F;
+ mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
+ mta |= (1 << hash_bit);
+ iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
+}
+
+/*
+ * Writes a value to a PHY register
+ * hw - Struct containing variables accessed by shared code
+ * reg_addr - address of the PHY register to write
+ * data - data to write to the PHY
+ */
+static s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
+{
+ int i;
+ u32 val;
+
+ val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
+ (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
+ MDIO_SUP_PREAMBLE |
+ MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
+ iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
+ ioread32(hw->hw_addr + REG_MDIO_CTRL);
+
+ for (i = 0; i < MDIO_WAIT_TIMES; i++) {
+ udelay(2);
+ val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
+ if (!(val & (MDIO_START | MDIO_BUSY)))
+ break;
+ }
+
+ if (!(val & (MDIO_START | MDIO_BUSY)))
+ return 0;
+
+ return ATLX_ERR_PHY;
+}
+
+/*
+ * Configures PHY autoneg and flow control advertisement settings
+ * hw - Struct containing variables accessed by shared code
+ */
+static s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
+{
+ s32 ret_val;
+ s16 mii_autoneg_adv_reg;
+ s16 mii_1000t_ctrl_reg;
+
+ /* Read the MII Auto-Neg Advertisement Register (Address 4). */
+ mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
+
+ /* Read the MII 1000Base-T Control Register (Address 9). */
+ mii_1000t_ctrl_reg = MII_ATLX_CR_1000T_DEFAULT_CAP_MASK;
+
+ /*
+ * First we clear all the 10/100 mb speed bits in the Auto-Neg
+ * Advertisement Register (Address 4) and the 1000 mb speed bits in
+ * the 1000Base-T Control Register (Address 9).
+ */
+ mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
+ mii_1000t_ctrl_reg &= ~MII_ATLX_CR_1000T_SPEED_MASK;
+
+ /*
+ * Need to parse media_type and set up
+ * the appropriate PHY registers.
+ */
+ switch (hw->media_type) {
+ case MEDIA_TYPE_AUTO_SENSOR:
+ mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
+ MII_AR_10T_FD_CAPS |
+ MII_AR_100TX_HD_CAPS |
+ MII_AR_100TX_FD_CAPS);
+ mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
+ hw->autoneg_advertised = ADVERTISE_10_HALF |
+ ADVERTISE_10_FULL |
+ ADVERTISE_100_HALF |
+ ADVERTISE_100_FULL |
+ ADVERTISE_1000_FULL;
+ break;
+
+ case MEDIA_TYPE_100M_FULL:
+ mii_1000t_ctrl_reg |= MII_AR_100TX_FD_CAPS;
+ hw->autoneg_advertised = ADVERTISE_100_FULL;
+ break;
+
+ case MEDIA_TYPE_100M_HALF:
+ mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
+ hw->autoneg_advertised = ADVERTISE_100_HALF;
+ break;
+
+ case MEDIA_TYPE_10M_FULL:
+ mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
+ hw->autoneg_advertised = ADVERTISE_10_FULL;
+ break;
+
+ default:
+ mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
+ hw->autoneg_advertised = ADVERTISE_10_HALF;
+ break;
+ }
+
+ /* flow control fixed to enable all */
+ mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
+
+ hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
+ hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
+
+ ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
+ if (ret_val)
+ return ret_val;
+
+ ret_val = atl1_write_phy_reg(hw, MII_ATLX_CR, mii_1000t_ctrl_reg);
+ if (ret_val)
+ return ret_val;
+
+ return 0;
+}
+
+static void atl1_init_flash_opcode(struct atl1_hw *hw)
+{
+ if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
+ /* Atmel */
+ hw->flash_vendor = 0;
+
+ /* Init OP table */
+ iowrite8(flash_table[hw->flash_vendor].cmd_program,
+ hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
+ iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
+ hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
+ iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
+ hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
+ iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
+ hw->hw_addr + REG_SPI_FLASH_OP_RDID);
+ iowrite8(flash_table[hw->flash_vendor].cmd_wren,
+ hw->hw_addr + REG_SPI_FLASH_OP_WREN);
+ iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
+ hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
+ iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
+ hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
+ iowrite8(flash_table[hw->flash_vendor].cmd_read,
+ hw->hw_addr + REG_SPI_FLASH_OP_READ);
+}
+
+static void atl1_init_pcie(struct atl1_hw *hw)
+{
+ u32 val;
+
+ val = LTSSM_TEST_MODE_DEF;
+ iowrite32(val, hw->hw_addr + REG_LTSSM_TEST_MODE);
+ val = ioread32(hw->hw_addr + REG_PCIE_PHY_MISC3);
+ val |= PCIE_PHY_MISC3_DS_PWR_DOWN;
+ iowrite32(val, hw->hw_addr + REG_PCIE_PHY_MISC3);
+}
+
+static bool atl1_check_cable(struct atl1_hw *hw)
+{
+ u16 pair_num;
+ u16 i;
+ u16 phy_val;
+
+ phy_val = 0x8000;
+ atl1_write_phy_reg(hw, MII_BMCR, phy_val);
+
+ for (pair_num = 0; pair_num < 4; pair_num++) {
+ phy_val = (u16) (pair_num << CDTC_PAIR_OFFSET);
+ phy_val |= CDTC_EN;
+ atl1_write_phy_reg(hw, MII_CDTC, phy_val);
+ for (i = 0; i < 200; i++) {
+ msleep(1);
+ atl1_read_phy_reg(hw, MII_CDTC, &phy_val);
+ if (!(phy_val & CDTC_EN))
+ break;
+ }
+ msleep(1);
+ atl1_read_phy_reg(hw, MII_CDTS, &phy_val);
+ if (((phy_val >> CDTS_STATUS_OFFSET) & 3) != CDTS_OPEN)
+ return true;
+ }
+ return false;
+}
+static s32 atl1_phy_commit(struct atl1_hw *hw)
+{
+ s32 retval;
+ u16 phy_data;
+ u32 val;
+ int i;
+
+ phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
+ retval = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
+ if (retval) {
+ for (i = 0; i < 25; i++) {
+ msleep(1);
+ val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
+ if (!(val & (MDIO_START | MDIO_BUSY)))
+ break;
+ }
+ if (val & (MDIO_START | MDIO_BUSY))
+ return retval;
+ }
+ return 0;
+}
+
+static s32 atl1_phy_init(struct atl1_hw *hw)
+{
+ u16 phy_data;
+ u16 i;
+ s32 retval;
+
+ if (hw->phy_configured)
+ return 0;
+
+ iowrite16(0, hw->hw_addr + REG_PHY_ENABLE);
+ msleep(2);
+ iowrite16(PHY_RESET, hw->hw_addr + REG_PHY_ENABLE);
+ msleep(2);
+
+ /* check for cable */
+ if (!atl1_check_cable(hw))
+ set_bit(0, &hw->force_ps);
+ else
+ clear_bit(0, &hw->force_ps);
+
+ /* enable PHY link change interrupt */
+ retval = atl1_write_phy_reg(hw, 18, 0xC00);
+ if (retval)
+ return retval;
+
+ /* setup autonegotiation parameters */
+ retval = atl1_phy_setup_autoneg_adv(hw);
+ if (retval)
+ return retval;
+
+ retval = atl1_phy_commit(hw);
+ if (retval)
+ return retval;
+
+ if (test_bit(0, &hw->force_ps)) {
+ atl1_write_phy_reg(hw, MII_DBG_ADDR, 0);
+ atl1_write_phy_reg(hw, MII_DBG_DATA, 0x124E);
+ atl1_write_phy_reg(hw, MII_DBG_ADDR, 1);
+ atl1_read_phy_reg(hw, MII_DBG_DATA, &phy_data);
+ phy_data |= 0x3;
+ atl1_write_phy_reg(hw, MII_DBG_DATA, phy_data);
+
+ for (i = 0; i < 15; i++)
+ msleep(100);
+ atl1_write_phy_reg(hw, MII_DBG_ADDR, 0);
+ atl1_write_phy_reg(hw, MII_DBG_DATA, 0x024E);
+ }
+ hw->phy_configured = true;
+ return retval;
+}
+
+/*
+ * Performs basic configuration of the adapter.
+ * hw - Struct containing variables accessed by shared code
+ * Assumes that the controller has previously been reset and is in a
+ * post-reset uninitialized state. Initializes multicast table,
+ * and Calls routines to setup link
+ * Leaves the transmit and receive units disabled and uninitialized.
+ */
+static s32 atl1_init_hw(struct atl1_hw *hw)
+{
+ u32 retval = 0;
+
+ atl1_init_pcie(hw);
+ iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
+ iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
+ atl1_init_flash_opcode(hw);
+ retval = atl1_phy_init(hw);
+
+ return retval;
+}
+
+/*
+ * Detects the current speed and duplex settings of the hardware.
+ * hw - Struct containing variables accessed by shared code
+ * speed - Speed of the connection
+ * duplex - Duplex setting of the connection
+ */
+static s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed,
+ u16 *duplex)
+{
+ struct pci_dev *pdev = hw->back->pdev;
+ s32 ret_val;
+ u16 phy_data;
+
+ /* ; --- Read PHY Specific Status Register (17) */
+ ret_val = atl1_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
+ if (ret_val)
+ return ret_val;
+
+ if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
+ return ATLX_ERR_PHY_RES;
+
+ switch (phy_data & MII_ATLX_PSSR_SPEED) {
+ case MII_ATLX_PSSR_1000MBS:
+ *speed = SPEED_1000;
+ break;
+ case MII_ATLX_PSSR_100MBS:
+ *speed = SPEED_100;
+ break;
+ case MII_ATLX_PSSR_10MBS:
+ *speed = SPEED_10;
+ break;
+ default:
+ dev_dbg(&pdev->dev, "error getting speed\n");
+ return ATLX_ERR_PHY_SPEED;
+ break;
+ }
+ if (phy_data & MII_ATLX_PSSR_DPLX)
+ *duplex = FULL_DUPLEX;
+ else
+ *duplex = HALF_DUPLEX;
+
+ return 0;
+}
+
+static void atl1_set_mac_addr(struct atl1_hw *hw)
+{
+ u32 value;
+ /*
+ * 00-0B-6A-F6-00-DC
+ * 0: 6AF600DC 1: 000B
+ * low dword
+ */
+ value = (((u32) hw->mac_addr[2]) << 24) |
+ (((u32) hw->mac_addr[3]) << 16) |
+ (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
+ iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
+ /* high dword */
+ value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
+ iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
+}
+
+static int atl1_alloc_queues(struct atl1_adapter *adapter)
+{
+ /* temporary placeholder function for NAPI */
+
+ return 0;
+}
+
+/*
* atl1_sw_init - Initialize general software structures (struct atl1_adapter)
* @adapter: board private structure to initialize
- *
- * atl1_sw_init initializes the Adapter private data structure.
- * Fields are initialized based on PCI device information and
- * OS network device settings (MTU size).
*/
static int __devinit atl1_sw_init(struct atl1_adapter *adapter)
{
struct atl1_hw *hw = &adapter->hw;
struct net_device *netdev = adapter->netdev;
+ int err;
hw->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
hw->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
@@ -121,6 +785,7 @@ static int __devinit atl1_sw_init(struct atl1_adapter *adapter)
adapter->ict = 50000; /* 100ms */
adapter->link_speed = SPEED_0; /* hardware init */
adapter->link_duplex = FULL_DUPLEX;
+ adapter->num_rx_queues = 1;
hw->phy_configured = false;
hw->preamble_len = 7;
@@ -143,7 +808,7 @@ static int __devinit atl1_sw_init(struct atl1_adapter *adapter)
hw->tx_jumbo_task_th = (hw->max_frame_size + 7) >> 3;
hw->tpd_fetch_gap = 1;
hw->rcb_value = atl1_rcb_64;
- hw->dma_ord = atl1_dma_ord_enh;
+ hw->dma_ord = atl1_dma_ord_out;
hw->dmar_block = atl1_dma_req_1024;
hw->dmaw_block = atl1_dma_req_1024;
hw->cmb_rrd = 4;
@@ -152,8 +817,16 @@ static int __devinit atl1_sw_init(struct atl1_adapter *adapter)
hw->cmb_tx_timer = 256; /* about 512us */
hw->smb_timer = 100000; /* about 200ms */
+ err = atl1_alloc_queues(adapter);
+ if (err) {
+ dev_printk(KERN_DEBUG, &adapter->pdev->dev,
+ "unable to allocate memory for queues\n");
+ return -ENOMEM;
+ }
+
spin_lock_init(&adapter->lock);
spin_lock_init(&adapter->mb_lock);
+ set_bit(__ATL1_DOWN, &adapter->flags);
return 0;
}
@@ -811,22 +1484,6 @@ static u32 atl1_configure(struct atl1_adapter *adapter)
}
/*
- * atl1_pcie_patch - Patch for PCIE module
- */
-static void atl1_pcie_patch(struct atl1_adapter *adapter)
-{
- u32 value;
-
- /* much vendor magic here */
- value = 0x6500;
- iowrite32(value, adapter->hw.hw_addr + 0x12FC);
- /* pcie flow control mode change */
- value = ioread32(adapter->hw.hw_addr + 0x1008);
- value |= 0x8000;
- iowrite32(value, adapter->hw.hw_addr + 0x1008);
-}
-
-/*
* When ACPI resume on some VIA MotherBoard, the Interrupt Disable bit/0x400
* on PCI Command register is disable.
* The function enable this bit.
@@ -2131,6 +2788,7 @@ static int __devinit atl1_probe(struct pci_dev *pdev,
err = -EIO;
goto err_pci_iomap;
}
+
/* get device revision number */
adapter->hw.dev_rev = ioread16(adapter->hw.hw_addr +
(REG_MASTER_CTRL + 2));
@@ -2169,26 +2827,11 @@ static int __devinit atl1_probe(struct pci_dev *pdev,
if (err)
goto err_common;
- netdev->features = NETIF_F_HW_CSUM;
- netdev->features |= NETIF_F_SG;
- netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
- netdev->features |= NETIF_F_TSO;
- netdev->features |= NETIF_F_LLTX;
+ netdev->features = NETIF_F_HW_CSUM | NETIF_F_SG | NETIF_F_TSO |
+ NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX | NETIF_F_LLTX;
- /*
- * patch for some L1 of old version,
- * the final version of L1 may not need these
- * patches
- */
- /* atl1_pcie_patch(adapter); */
-
- /* really reset GPHY core */
- iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
+ atl1_phy_init(&adapter->hw);
- /*
- * reset the controller to
- * put the device in a known good starting state
- */
if (atl1_reset_hw(&adapter->hw)) {
err = -EIO;
goto err_common;
@@ -2205,18 +2848,6 @@ static int __devinit atl1_probe(struct pci_dev *pdev,
atl1_check_options(adapter);
- /* pre-init the MAC, and setup link */
- err = atl1_init_hw(&adapter->hw);
- if (err) {
- err = -EIO;
- goto err_common;
- }
-
- atl1_pcie_patch(adapter);
- /* assume we have no link for now */
- netif_carrier_off(netdev);
- netif_stop_queue(netdev);
-
init_timer(&adapter->watchdog_timer);
adapter->watchdog_timer.function = &atl1_watchdog;
adapter->watchdog_timer.data = (unsigned long)adapter;
@@ -2236,8 +2867,11 @@ static int __devinit atl1_probe(struct pci_dev *pdev,
if (err)
goto err_common;
+ netif_carrier_off(netdev);
+ netif_stop_queue(netdev);
+
cards_found++;
- atl1_via_workaround(adapter);
+
return 0;
err_common:
@@ -2852,662 +3486,3 @@ const struct ethtool_ops atl1_ethtool_ops = {
.get_sset_count = atl1_get_sset_count,
.set_tso = ethtool_op_set_tso,
};
-
-/*
- * Reset the transmit and receive units; mask and clear all interrupts.
- * hw - Struct containing variables accessed by shared code
- * return : 0 or idle status (if error)
- */
-s32 atl1_reset_hw(struct atl1_hw *hw)
-{
- struct pci_dev *pdev = hw->back->pdev;
- u32 icr;
- int i;
-
- /*
- * Issue Soft Reset to the MAC. This will reset the chip's
- * transmit, receive, DMA. It will not effect
- * the current PCI configuration. The global reset bit is self-
- * clearing, and should clear within a microsecond.
- */
- iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
- ioread32(hw->hw_addr + REG_MASTER_CTRL);
-
- /* delay about 1ms */
- msleep(1);
-
- /* wait at least 10ms for idle */
- for (i = 0; i < 10; i++) {
- icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
- if (!icr)
- break;
- /* delay 1 ms */
- msleep(1);
- cpu_relax();
- }
-
- if (icr) {
- dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr);
- return icr;
- }
-
- return 0;
-}
-
-/* function about EEPROM
- *
- * check_eeprom_exist
- * return 0 if eeprom exist
- */
-static int atl1_check_eeprom_exist(struct atl1_hw *hw)
-{
- u32 value;
-
- value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
- if (value & SPI_FLASH_CTRL_EN_VPD) {
- value &= ~SPI_FLASH_CTRL_EN_VPD;
- iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
- }
-
- value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
- return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
-}
-
-static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
-{
- int i;
- u32 control;
-
- if (offset & 3)
- /* address do not align */
- return false;
-
- iowrite32(0, hw->hw_addr + REG_VPD_DATA);
- control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
- iowrite32(control, hw->hw_addr + REG_VPD_CAP);
- ioread32(hw->hw_addr + REG_VPD_CAP);
-
- for (i = 0; i < 10; i++) {
- msleep(2);
- control = ioread32(hw->hw_addr + REG_VPD_CAP);
- if (control & VPD_CAP_VPD_FLAG)
- break;
- }
- if (control & VPD_CAP_VPD_FLAG) {
- *p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
- return true;
- }
- /* timeout */
- return false;
-}
-
-/*
- * Reads the value from a PHY register
- * hw - Struct containing variables accessed by shared code
- * reg_addr - address of the PHY register to read
- */
-s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
-{
- u32 val;
- int i;
-
- val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
- MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
- MDIO_CLK_SEL_SHIFT;
- iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
- ioread32(hw->hw_addr + REG_MDIO_CTRL);
-
- for (i = 0; i < MDIO_WAIT_TIMES; i++) {
- udelay(2);
- val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
- if (!(val & (MDIO_START | MDIO_BUSY)))
- break;
- }
- if (!(val & (MDIO_START | MDIO_BUSY))) {
- *phy_data = (u16) val;
- return 0;
- }
- return ATLX_ERR_PHY;
-}
-
-#define CUSTOM_SPI_CS_SETUP 2
-#define CUSTOM_SPI_CLK_HI 2
-#define CUSTOM_SPI_CLK_LO 2
-#define CUSTOM_SPI_CS_HOLD 2
-#define CUSTOM_SPI_CS_HI 3
-
-static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
-{
- int i;
- u32 value;
-
- iowrite32(0, hw->hw_addr + REG_SPI_DATA);
- iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
-
- value = SPI_FLASH_CTRL_WAIT_READY |
- (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
- SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
- SPI_FLASH_CTRL_CLK_HI_MASK) <<
- SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
- SPI_FLASH_CTRL_CLK_LO_MASK) <<
- SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
- SPI_FLASH_CTRL_CS_HOLD_MASK) <<
- SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
- SPI_FLASH_CTRL_CS_HI_MASK) <<
- SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
- SPI_FLASH_CTRL_INS_SHIFT;
-
- iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
-
- value |= SPI_FLASH_CTRL_START;
- iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
- ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
-
- for (i = 0; i < 10; i++) {
- msleep(1);
- value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
- if (!(value & SPI_FLASH_CTRL_START))
- break;
- }
-
- if (value & SPI_FLASH_CTRL_START)
- return false;
-
- *buf = ioread32(hw->hw_addr + REG_SPI_DATA);
-
- return true;
-}
-
-/*
- * get_permanent_address
- * return 0 if get valid mac address,
- */
-static int atl1_get_permanent_address(struct atl1_hw *hw)
-{
- u32 addr[2];
- u32 i, control;
- u16 reg;
- u8 eth_addr[ETH_ALEN];
- bool key_valid;
-
- if (is_valid_ether_addr(hw->perm_mac_addr))
- return 0;
-
- /* init */
- addr[0] = addr[1] = 0;
-
- if (!atl1_check_eeprom_exist(hw)) {
- reg = 0;
- key_valid = false;
- /* Read out all EEPROM content */
- i = 0;
- while (1) {
- if (atl1_read_eeprom(hw, i + 0x100, &control)) {
- if (key_valid) {
- if (reg == REG_MAC_STA_ADDR)
- addr[0] = control;
- else if (reg == (REG_MAC_STA_ADDR + 4))
- addr[1] = control;
- key_valid = false;
- } else if ((control & 0xff) == 0x5A) {
- key_valid = true;
- reg = (u16) (control >> 16);
- } else
- break;
- } else
- /* read error */
- break;
- i += 4;
- }
-
- *(u32 *) ð_addr[2] = swab32(addr[0]);
- *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]);
- if (is_valid_ether_addr(eth_addr)) {
- memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
- return 0;
- }
- return 1;
- }
-
- /* see if SPI FLAGS exist ? */
- addr[0] = addr[1] = 0;
- reg = 0;
- key_valid = false;
- i = 0;
- while (1) {
- if (atl1_spi_read(hw, i + 0x1f000, &control)) {
- if (key_valid) {
- if (reg == REG_MAC_STA_ADDR)
- addr[0] = control;
- else if (reg == (REG_MAC_STA_ADDR + 4))
- addr[1] = control;
- key_valid = false;
- } else if ((control & 0xff) == 0x5A) {
- key_valid = true;
- reg = (u16) (control >> 16);
- } else
- /* data end */
- break;
- } else
- /* read error */
- break;
- i += 4;
- }
-
- *(u32 *) ð_addr[2] = swab32(addr[0]);
- *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]);
- if (is_valid_ether_addr(eth_addr)) {
- memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
- return 0;
- }
-
- /*
- * On some motherboards, the MAC address is written by the
- * BIOS directly to the MAC register during POST, and is
- * not stored in eeprom. If all else thus far has failed
- * to fetch the permanent MAC address, try reading it directly.
- */
- addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
- addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
- *(u32 *) ð_addr[2] = swab32(addr[0]);
- *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]);
- if (is_valid_ether_addr(eth_addr)) {
- memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
- return 0;
- }
-
- return 1;
-}
-
-/*
- * Reads the adapter's MAC address from the EEPROM
- * hw - Struct containing variables accessed by shared code
- */
-s32 atl1_read_mac_addr(struct atl1_hw *hw)
-{
- u16 i;
-
- if (atl1_get_permanent_address(hw))
- random_ether_addr(hw->perm_mac_addr);
-
- for (i = 0; i < ETH_ALEN; i++)
- hw->mac_addr[i] = hw->perm_mac_addr[i];
- return 0;
-}
-
-/*
- * Hashes an address to determine its location in the multicast table
- * hw - Struct containing variables accessed by shared code
- * mc_addr - the multicast address to hash
- *
- * atl1_hash_mc_addr
- * purpose
- * set hash value for a multicast address
- * hash calcu processing :
- * 1. calcu 32bit CRC for multicast address
- * 2. reverse crc with MSB to LSB
- */
-u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
-{
- u32 crc32, value = 0;
- int i;
-
- crc32 = ether_crc_le(6, mc_addr);
- for (i = 0; i < 32; i++)
- value |= (((crc32 >> i) & 1) << (31 - i));
-
- return value;
-}
-
-/*
- * Sets the bit in the multicast table corresponding to the hash value.
- * hw - Struct containing variables accessed by shared code
- * hash_value - Multicast address hash value
- */
-void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
-{
- u32 hash_bit, hash_reg;
- u32 mta;
-
- /*
- * The HASH Table is a register array of 2 32-bit registers.
- * It is treated like an array of 64 bits. We want to set
- * bit BitArray[hash_value]. So we figure out what register
- * the bit is in, read it, OR in the new bit, then write
- * back the new value. The register is determined by the
- * upper 7 bits of the hash value and the bit within that
- * register are determined by the lower 5 bits of the value.
- */
- hash_reg = (hash_value >> 31) & 0x1;
- hash_bit = (hash_value >> 26) & 0x1F;
- mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
- mta |= (1 << hash_bit);
- iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
-}
-
-/*
- * Writes a value to a PHY register
- * hw - Struct containing variables accessed by shared code
- * reg_addr - address of the PHY register to write
- * data - data to write to the PHY
- */
-s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
-{
- int i;
- u32 val;
-
- val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
- (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
- MDIO_SUP_PREAMBLE |
- MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
- iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
- ioread32(hw->hw_addr + REG_MDIO_CTRL);
-
- for (i = 0; i < MDIO_WAIT_TIMES; i++) {
- udelay(2);
- val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
- if (!(val & (MDIO_START | MDIO_BUSY)))
- break;
- }
-
- if (!(val & (MDIO_START | MDIO_BUSY)))
- return 0;
-
- return ATLX_ERR_PHY;
-}
-
-/*
- * Configures PHY autoneg and flow control advertisement settings
- * hw - Struct containing variables accessed by shared code
- */
-s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
-{
- s32 ret_val;
- s16 mii_autoneg_adv_reg;
- s16 mii_1000t_ctrl_reg;
-
- /* Read the MII Auto-Neg Advertisement Register (Address 4). */
- mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
-
- /* Read the MII 1000Base-T Control Register (Address 9). */
- mii_1000t_ctrl_reg = MII_ATLX_CR_1000T_DEFAULT_CAP_MASK;
-
- /*
- * First we clear all the 10/100 mb speed bits in the Auto-Neg
- * Advertisement Register (Address 4) and the 1000 mb speed bits in
- * the 1000Base-T Control Register (Address 9).
- */
- mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
- mii_1000t_ctrl_reg &= ~MII_ATLX_CR_1000T_SPEED_MASK;
-
- /*
- * Need to parse media_type and set up
- * the appropriate PHY registers.
- */
- switch (hw->media_type) {
- case MEDIA_TYPE_AUTO_SENSOR:
- mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
- MII_AR_10T_FD_CAPS |
- MII_AR_100TX_HD_CAPS |
- MII_AR_100TX_FD_CAPS);
- mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
- hw->autoneg_advertised = ADVERTISE_10_HALF |
- ADVERTISE_10_FULL |
- ADVERTISE_100_HALF |
- ADVERTISE_100_FULL |
- ADVERTISE_1000_FULL;
- break;
-
- case MEDIA_TYPE_100M_FULL:
- mii_1000t_ctrl_reg |= MII_AR_100TX_FD_CAPS;
- hw->autoneg_advertised = ADVERTISE_100_FULL;
- break;
-
- case MEDIA_TYPE_100M_HALF:
- mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
- hw->autoneg_advertised = ADVERTISE_100_HALF;
- break;
-
- case MEDIA_TYPE_10M_FULL:
- mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
- hw->autoneg_advertised = ADVERTISE_10_FULL;
- break;
-
- default:
- mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
- hw->autoneg_advertised = ADVERTISE_10_HALF;
- break;
- }
-
- /* flow control fixed to enable all */
- mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
-
- hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
- hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
-
- ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
- if (ret_val)
- return ret_val;
-
- ret_val = atl1_write_phy_reg(hw, MII_ATLX_CR, mii_1000t_ctrl_reg);
- if (ret_val)
- return ret_val;
-
- return 0;
-}
-
-static void atl1_init_flash_opcode(struct atl1_hw *hw)
-{
- if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
- /* Atmel */
- hw->flash_vendor = 0;
-
- /* Init OP table */
- iowrite8(flash_table[hw->flash_vendor].cmd_program,
- hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
- iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
- hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
- iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
- hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
- iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
- hw->hw_addr + REG_SPI_FLASH_OP_RDID);
- iowrite8(flash_table[hw->flash_vendor].cmd_wren,
- hw->hw_addr + REG_SPI_FLASH_OP_WREN);
- iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
- hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
- iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
- hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
- iowrite8(flash_table[hw->flash_vendor].cmd_read,
- hw->hw_addr + REG_SPI_FLASH_OP_READ);
-}
-
-static void atl1_init_pcie(struct atl1_hw *hw)
-{
- u32 val;
-
- val = LTSSM_TEST_MODE_DEF;
- iowrite32(val, hw->hw_addr + REG_LTSSM_TEST_MODE);
- val = ioread32(hw->hw_addr + REG_PCIE_PHY_MISC3);
- val |= PCIE_PHY_MISC3_DS_PWR_DOWN;
- iowrite32(val, hw->hw_addr + REG_PCIE_PHY_MISC3);
-}
-
-static bool atl1_check_cable(struct atl1_hw *hw)
-{
- u16 pair_num;
- u16 i;
- u16 phy_val;
-
- phy_val = 0x8000;
- atl1_write_phy_reg(hw, MII_BMCR, phy_val);
-
- for (pair_num = 0; pair_num < 4; pair_num++) {
- phy_val = (u16) (pair_num << CDTC_PAIR_OFFSET);
- phy_val |= CDTC_EN;
- atl1_write_phy_reg(hw, MII_CDTC, phy_val);
- for (i = 0; i < 200; i++) {
- msleep(1);
- atl1_read_phy_reg(hw, MII_CDTC, &phy_val);
- if (!(phy_val & CDTC_EN))
- break;
- }
- msleep(1);
- atl1_read_phy_reg(hw, MII_CDTS, &phy_val);
- if (((phy_val >> CDTS_STATUS_OFFSET) & 3) != CDTS_OPEN)
- return true;
- }
- return false;
-}
-static s32 atl1_phy_commit(struct atl1_hw *hw)
-{
- s32 retval;
- u16 phy_data;
- u32 val;
- int i;
-
- phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
- retval = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
- if (retval) {
- for (i = 0; i < 25; i++) {
- msleep(1);
- val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
- if (!(val & (MDIO_START | MDIO_BUSY)))
- break;
- }
- if (val & (MDIO_START | MDIO_BUSY))
- return retval;
- }
- return 0;
-}
-
-static s32 atl1_phy_init(struct atl1_hw *hw)
-{
- u16 phy_data;
- u16 i;
- s32 retval;
-
- if (hw->phy_configured)
- return 0;
-
- iowrite16(0, hw->hw_addr + REG_PHY_ENABLE);
- msleep(2);
- iowrite16(PHY_RESET, hw->hw_addr + REG_PHY_ENABLE);
- msleep(2);
-
- /* check for cable */
- if (!atl1_check_cable(hw))
- set_bit(0, &hw->force_ps);
- else
- clear_bit(0, &hw->force_ps);
-
- /* enable PHY link change interrupt */
- retval = atl1_write_phy_reg(hw, 18, 0xC00);
- if (retval)
- return retval;
-
- /* setup autonegotiation parameters */
- retval = atl1_phy_setup_autoneg_adv(hw);
- if (retval)
- return retval;
-
- retval = atl1_phy_commit(hw);
- if (retval)
- return retval;
-
- if (test_bit(0, &hw->force_ps)) {
- atl1_write_phy_reg(hw, MII_DBG_ADDR, 0);
- atl1_write_phy_reg(hw, MII_DBG_DATA, 0x124E);
- atl1_write_phy_reg(hw, MII_DBG_ADDR, 1);
- atl1_read_phy_reg(hw, MII_DBG_DATA, &phy_data);
- phy_data |= 0x3;
- atl1_write_phy_reg(hw, MII_DBG_DATA, phy_data);
-
- for (i = 0; i < 15; i++)
- msleep(100);
- atl1_write_phy_reg(hw, MII_DBG_ADDR, 0);
- atl1_write_phy_reg(hw, MII_DBG_DATA, 0x024E);
- }
- hw->phy_configured = true;
- return retval;
-}
-
-/*
- * Performs basic configuration of the adapter.
- * hw - Struct containing variables accessed by shared code
- * Assumes that the controller has previously been reset and is in a
- * post-reset uninitialized state. Initializes multicast table,
- * and Calls routines to setup link
- * Leaves the transmit and receive units disabled and uninitialized.
- */
-s32 atl1_init_hw(struct atl1_hw *hw)
-{
- u32 retval = 0;
-
- atl1_init_pcie(hw);
- iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
- iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
- atl1_init_flash_opcode(hw);
- retval = atl1_phy_init(hw);
-
- return retval;
-}
-
-/*
- * Detects the current speed and duplex settings of the hardware.
- * hw - Struct containing variables accessed by shared code
- * speed - Speed of the connection
- * duplex - Duplex setting of the connection
- */
-s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
-{
- struct pci_dev *pdev = hw->back->pdev;
- s32 ret_val;
- u16 phy_data;
-
- /* ; --- Read PHY Specific Status Register (17) */
- ret_val = atl1_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
- if (ret_val)
- return ret_val;
-
- if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
- return ATLX_ERR_PHY_RES;
-
- switch (phy_data & MII_ATLX_PSSR_SPEED) {
- case MII_ATLX_PSSR_1000MBS:
- *speed = SPEED_1000;
- break;
- case MII_ATLX_PSSR_100MBS:
- *speed = SPEED_100;
- break;
- case MII_ATLX_PSSR_10MBS:
- *speed = SPEED_10;
- break;
- default:
- dev_dbg(&pdev->dev, "error getting speed\n");
- return ATLX_ERR_PHY_SPEED;
- break;
- }
- if (phy_data & MII_ATLX_PSSR_DPLX)
- *duplex = FULL_DUPLEX;
- else
- *duplex = HALF_DUPLEX;
-
- return 0;
-}
-
-void atl1_set_mac_addr(struct atl1_hw *hw)
-{
- u32 value;
- /*
- * 00-0B-6A-F6-00-DC
- * 0: 6AF600DC 1: 000B
- * low dword
- */
- value = (((u32) hw->mac_addr[2]) << 24) |
- (((u32) hw->mac_addr[3]) << 16) |
- (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
- iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
- /* high dword */
- value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
- iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
-}
diff --git a/drivers/net/atlx/atl1.h b/drivers/net/atlx/atl1.h
index c1b99f2..2c2570e 100644
--- a/drivers/net/atlx/atl1.h
+++ b/drivers/net/atlx/atl1.h
@@ -56,25 +56,13 @@ struct atl1_adapter;
struct atl1_hw;
/* function prototypes needed by multiple files */
-s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw);
-s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data);
-s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex);
-s32 atl1_read_mac_addr(struct atl1_hw *hw);
-s32 atl1_init_hw(struct atl1_hw *hw);
-s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex);
-s32 atl1_set_speed_and_duplex(struct atl1_hw *hw, u16 speed, u16 duplex);
-u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr);
-void atl1_hash_set(struct atl1_hw *hw, u32 hash_value);
-s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data);
-void atl1_set_mac_addr(struct atl1_hw *hw);
-s32 atl1_phy_enter_power_saving(struct atl1_hw *hw);
-s32 atl1_reset_hw(struct atl1_hw *hw);
-void atl1_check_options(struct atl1_adapter *adapter);
+static u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr);
+static void atl1_hash_set(struct atl1_hw *hw, u32 hash_value);
+static s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data);
+static void atl1_set_mac_addr(struct atl1_hw *hw);
static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
int cmd);
static u32 atl1_check_link(struct atl1_adapter *adapter);
-void atl1_down(struct atl1_adapter *adapter);
-int atl1_reset(struct atl1_adapter *adapter);
extern const struct ethtool_ops atl1_ethtool_ops;
@@ -806,6 +794,7 @@ struct atl1_adapter {
struct atl1_smb smb;
struct atl1_cmb cmb;
unsigned long flags;
+ int num_rx_queues;
};
enum atl1_state {
--
1.5.3.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 13/26] atl1: refactor interrupt handling
2008-01-01 2:22 [PATCH 00/26] atl1: divide and modernize Jay Cliburn
` (11 preceding siblings ...)
2008-01-01 2:22 ` [PATCH 12/26] atl1: refactor atl1_probe Jay Cliburn
@ 2008-01-01 2:22 ` Jay Cliburn
2008-01-01 2:22 ` [PATCH 14/26] atl1: move stray defines to header file Jay Cliburn
` (13 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Jay Cliburn @ 2008-01-01 2:22 UTC (permalink / raw)
To: netdev; +Cc: Jay Cliburn
Refactor interrupt handling to conform with the current vendor driver
version 1.2.40.2.
Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net>
---
drivers/net/atlx/atl1.c | 196 ++++++++++++++++++++++-------------------------
drivers/net/atlx/atl1.h | 25 +++++-
drivers/net/atlx/atlx.c | 2 +-
3 files changed, 114 insertions(+), 109 deletions(-)
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index d38f26f..9c86ef4 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -1740,12 +1740,11 @@ next:
return num_alloc;
}
-static void atl1_intr_rx(struct atl1_adapter *adapter)
+static void atl1_clean_rx_irq(struct atl1_adapter *adapter)
{
+ struct net_device *netdev = adapter->netdev;
int i, count;
- u16 length;
- u16 rrd_next_to_clean;
- u32 value;
+ u16 length, rrd_next_to_clean;
struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
struct atl1_buffer *buffer_info;
@@ -1754,7 +1753,7 @@ static void atl1_intr_rx(struct atl1_adapter *adapter)
count = 0;
- rrd_next_to_clean = atomic_read(&rrd_ring->next_to_clean);
+ rrd_next_to_clean = (u16) atomic_read(&rrd_ring->next_to_clean);
while (1) {
rrd = ATL1_RRD_DESC(rrd_ring, rrd_next_to_clean);
@@ -1795,6 +1794,7 @@ chk_rrd:
/* bad rrd */
dev_printk(KERN_DEBUG, &adapter->pdev->dev,
"bad RRD\n");
+
/* see if update RFD index */
if (rrd->num_buf > 1)
atl1_update_rfd_index(adapter, rrd);
@@ -1823,13 +1823,18 @@ rrd_ok:
count++;
if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
- if (!(rrd->err_flg &
- (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM
- | ERR_FLAG_LEN))) {
- /* packet error, don't need upstream */
- buffer_info->alloced = 0;
- rrd->xsz.valid = 0;
- continue;
+ if (rrd->err_flg & (ERR_FLAG_CRC | ERR_FLAG_TRUNC |
+ ERR_FLAG_CODE | ERR_FLAG_OV)) {
+ if (!(netdev->flags & IFF_PROMISC)) {
+ /* packet error, don't need upstream */
+ buffer_info->alloced = 0;
+ rrd->xsz.valid = 0;
+ dev_printk(KERN_DEBUG,
+ &adapter->pdev->dev,
+ "rrd error flag 0x%08X\n",
+ rrd->err_flg);
+ continue;
+ }
}
}
@@ -1862,33 +1867,13 @@ rrd_ok:
}
atomic_set(&rrd_ring->next_to_clean, rrd_next_to_clean);
-
atl1_alloc_rx_buffers(adapter);
- /* update mailbox ? */
- if (count) {
- u32 tpd_next_to_use;
- u32 rfd_next_to_use;
-
- spin_lock(&adapter->mb_lock);
-
- tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
- rfd_next_to_use =
- atomic_read(&adapter->rfd_ring.next_to_use);
- rrd_next_to_clean =
- atomic_read(&adapter->rrd_ring.next_to_clean);
- value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
- MB_RFD_PROD_INDX_SHIFT) |
- ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
- MB_RRD_CONS_INDX_SHIFT) |
- ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
- MB_TPD_PROD_INDX_SHIFT);
- iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
- spin_unlock(&adapter->mb_lock);
- }
+ if (count)
+ atl1_update_mailbox(adapter);
}
-static void atl1_intr_tx(struct atl1_adapter *adapter)
+static bool atl1_clean_tx_irq(struct atl1_adapter *adapter)
{
struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
struct atl1_buffer *buffer_info;
@@ -1905,7 +1890,7 @@ static void atl1_intr_tx(struct atl1_adapter *adapter)
buffer_info = &tpd_ring->buffer_info[sw_tpd_next_to_clean];
if (buffer_info->dma) {
pci_unmap_page(adapter->pdev, buffer_info->dma,
- buffer_info->length, PCI_DMA_TODEVICE);
+ buffer_info->length, PCI_DMA_TODEVICE);
buffer_info->dma = 0;
}
@@ -1922,6 +1907,11 @@ static void atl1_intr_tx(struct atl1_adapter *adapter)
if (netif_queue_stopped(adapter->netdev)
&& netif_carrier_ok(adapter->netdev))
netif_wake_queue(adapter->netdev);
+
+ if (sw_tpd_next_to_clean == (u16) atomic_read(&tpd_ring->next_to_use))
+ return true;
+ else
+ return false;
}
static u16 atl1_tpd_avail(struct atl1_tpd_ring *tpd_ring)
@@ -2285,80 +2275,75 @@ static int atl1_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
static irqreturn_t atl1_intr(int irq, void *data)
{
struct atl1_adapter *adapter = netdev_priv(data);
+ struct atl1_hw *hw = &adapter->hw;
u32 status;
- u8 update_rx;
int max_ints = 10;
status = adapter->cmb.cmb->int_stats;
if (!status)
return IRQ_NONE;
- update_rx = 0;
-
- do {
- /* clear CMB interrupt status at once */
- adapter->cmb.cmb->int_stats = 0;
-
- if (status & ISR_GPHY) /* clear phy status */
- atlx_clear_phy_int(adapter);
+loopint:
+ /* clear CMB interrupt status at once */
+ adapter->cmb.cmb->int_stats = 0;
- /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
- iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR);
+ if (status & ISR_GPHY) /* clear phy status */
+ atlx_clear_phy_int(adapter);
- /* check if SMB intr */
- if (status & ISR_SMB)
- atl1_inc_smb(adapter);
+ /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
+ status |= (ISR_DIS_INT | ISR_DIS_DMA);
+ iowrite32(status, adapter->hw.hw_addr + REG_ISR);
- /* check if PCIE PHY Link down */
- if (status & ISR_PHY_LINKDOWN) {
- dev_printk(KERN_DEBUG, &adapter->pdev->dev,
- "pcie phy link down %x\n", status);
- if (netif_running(adapter->netdev)) { /* reset MAC */
- iowrite32(0, adapter->hw.hw_addr + REG_IMR);
- schedule_work(&adapter->pcie_dma_to_rst_task);
- return IRQ_HANDLED;
- }
- }
-
- /* check if DMA read/write error ? */
- if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
- dev_printk(KERN_DEBUG, &adapter->pdev->dev,
- "pcie DMA r/w error (status = 0x%x)\n",
- status);
- iowrite32(0, adapter->hw.hw_addr + REG_IMR);
- schedule_work(&adapter->pcie_dma_to_rst_task);
+ /* check if PCIE PHY Link down */
+ if (status & ISR_PHY_LINKDOWN) {
+ dev_printk(KERN_DEBUG, &adapter->pdev->dev,
+ "pcie phy link down %x\n", status);
+ if (netif_running(adapter->netdev)) {
+ /* reset MAC */
+ iowrite32(0, hw->hw_addr + REG_ISR);
+ iowrite32(0, hw->hw_addr + REG_IMR);
+ ioread32(hw->hw_addr + REG_IMR);
+ schedule_work(&adapter->reset_task);
return IRQ_HANDLED;
}
+ }
- /* link event */
- if (status & ISR_GPHY) {
- adapter->soft_stats.tx_carrier_errors++;
- atl1_check_for_link(adapter);
- }
+ /* check if DMA read/write error ? */
+ if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
+ dev_printk(KERN_DEBUG, &adapter->pdev->dev,
+ "pcie DMA r/w error (status = 0x%x)\n",
+ status);
+ iowrite32(0, hw->hw_addr + REG_ISR);
+ iowrite32(0, hw->hw_addr + REG_IMR);
+ ioread32(hw->hw_addr + REG_IMR);
+ schedule_work(&adapter->reset_task);
+ return IRQ_HANDLED;
+ }
- /* transmit event */
- if (status & ISR_CMB_TX)
- atl1_intr_tx(adapter);
-
- /* rx exception */
- if (unlikely(status & (ISR_RXF_OV | ISR_RFD_UNRUN |
- ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
- ISR_HOST_RRD_OV | ISR_CMB_RX))) {
- if (status & (ISR_RXF_OV | ISR_RFD_UNRUN |
- ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
- ISR_HOST_RRD_OV))
- dev_printk(KERN_DEBUG, &adapter->pdev->dev,
- "rx exception, ISR = 0x%x\n", status);
- atl1_intr_rx(adapter);
- }
+ /* check if SMB intr */
+ if (status & ISR_SMB)
+ atl1_inc_smb(adapter);
- if (--max_ints < 0)
- break;
+ /* link event */
+ if (status & (ISR_GPHY | ISR_MANUAL)) {
+ adapter->soft_stats.tx_carrier_errors++;
+ atl1_check_for_link(adapter);
+ }
+
+ /* transmit event */
+ if (status & ISR_TX_EVENT)
+ atl1_clean_tx_irq(adapter);
- } while ((status = adapter->cmb.cmb->int_stats));
+ /* rx event */
+ if (status & ISR_RX_EVENT)
+ atl1_clean_rx_irq(adapter);
- /* re-enable Interrupt */
- iowrite32(ISR_DIS_SMB | ISR_DIS_DMA, adapter->hw.hw_addr + REG_ISR);
+ status = adapter->cmb.cmb->int_stats;
+ if ((--max_ints > 0) && status)
+ goto loopint;
+
+ /* re-enable interrupts */
+ iowrite32((ISR_DIS_SMB | ISR_DIS_DMA), adapter->hw.hw_addr + REG_ISR);
return IRQ_HANDLED;
}
@@ -2460,16 +2445,22 @@ void atl1_down(struct atl1_adapter *adapter)
atl1_clean_rx_ring(adapter);
}
-static void atl1_tx_timeout_task(struct work_struct *work)
+static void atl1_reinit_locked(struct atl1_adapter *adapter)
{
- struct atl1_adapter *adapter =
- container_of(work, struct atl1_adapter, tx_timeout_task);
- struct net_device *netdev = adapter->netdev;
-
- netif_device_detach(netdev);
+ WARN_ON(in_interrupt());
+ while (test_and_set_bit(__ATL1_RESETTING, &adapter->flags))
+ msleep(1);
atl1_down(adapter);
atl1_up(adapter);
- netif_device_attach(netdev);
+ clear_bit(__ATL1_RESETTING, &adapter->flags);
+}
+
+static void atl1_reset_task(struct work_struct *work)
+{
+ struct atl1_adapter *adapter;
+
+ adapter = container_of(work, struct atl1_adapter, reset_task);
+ atl1_reinit_locked(adapter);
}
/*
@@ -2857,12 +2848,9 @@ static int __devinit atl1_probe(struct pci_dev *pdev,
adapter->phy_config_timer.data = (unsigned long)adapter;
adapter->phy_timer_pending = false;
- INIT_WORK(&adapter->tx_timeout_task, atl1_tx_timeout_task);
-
+ INIT_WORK(&adapter->reset_task, atl1_reset_task);
INIT_WORK(&adapter->link_chg_task, atlx_link_chg_task);
- INIT_WORK(&adapter->pcie_dma_to_rst_task, atl1_tx_timeout_task);
-
err = register_netdev(netdev);
if (err)
goto err_common;
diff --git a/drivers/net/atlx/atl1.h b/drivers/net/atlx/atl1.h
index 2c2570e..8198f82 100644
--- a/drivers/net/atlx/atl1.h
+++ b/drivers/net/atlx/atl1.h
@@ -262,7 +262,7 @@ extern const struct ethtool_ops atl1_ethtool_ops;
#define ISR_RRD_OV 0x20
#define ISR_TXF_UNRUN 0x40
#define ISR_LINK 0x80
-#define ISR_HOST_RFD_UNRUN 0x100
+#define ISR_HOST_RFD_UR 0x100
#define ISR_HOST_RRD_OV 0x200
#define ISR_DMAR_TO_RST 0x400
#define ISR_DMAW_TO_RST 0x800
@@ -288,6 +288,24 @@ extern const struct ethtool_ops atl1_ethtool_ops;
ISR_CMB_TX |\
ISR_CMB_RX)
+#define ISR_TX_EVENT (\
+ ISR_TXF_UNRUN |\
+ ISR_TX_PKT |\
+ ISR_TX_DMA |\
+ ISR_CMB_TX |\
+ ISR_MAC_TX)
+
+#define ISR_RX_EVENT (\
+ ISR_RXF_OV |\
+ ISR_RFD_UNRUN |\
+ ISR_RRD_OV |\
+ ISR_HOST_RFD_UR |\
+ ISR_HOST_RRD_OV |\
+ ISR_RX_PKT |\
+ ISR_RX_DMA |\
+ ISR_CMB_RX |\
+ ISR_MAC_RX)
+
/* Debug Interrupt Mask (enable all interrupt) */
#define IMR_DEBUG_MASK (\
ISR_SMB |\
@@ -762,10 +780,8 @@ struct atl1_adapter {
u32 wol;
u16 link_speed;
u16 link_duplex;
- spinlock_t lock;
- struct work_struct tx_timeout_task;
+ struct work_struct reset_task;
struct work_struct link_chg_task;
- struct work_struct pcie_dma_to_rst_task;
struct timer_list watchdog_timer;
struct timer_list phy_config_timer;
bool phy_timer_pending;
@@ -776,6 +792,7 @@ struct atl1_adapter {
/* TX */
struct atl1_tpd_ring tpd_ring;
spinlock_t mb_lock;
+ spinlock_t lock;
/* RX */
struct atl1_rfd_ring rfd_ring;
diff --git a/drivers/net/atlx/atlx.c b/drivers/net/atlx/atlx.c
index 354050f..18c2d7e 100644
--- a/drivers/net/atlx/atlx.c
+++ b/drivers/net/atlx/atlx.c
@@ -204,7 +204,7 @@ static void atlx_tx_timeout(struct net_device *netdev)
{
struct atlx_adapter *adapter = netdev_priv(netdev);
/* Do the reset outside of interrupt context */
- schedule_work(&adapter->tx_timeout_task);
+ schedule_work(&adapter->reset_task);
}
/*
--
1.5.3.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 14/26] atl1: move stray defines to header file
2008-01-01 2:22 [PATCH 00/26] atl1: divide and modernize Jay Cliburn
` (12 preceding siblings ...)
2008-01-01 2:22 ` [PATCH 13/26] atl1: refactor interrupt handling Jay Cliburn
@ 2008-01-01 2:22 ` Jay Cliburn
2008-01-01 2:22 ` [PATCH 15/26] atl1: tidy up ring management Jay Cliburn
` (12 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Jay Cliburn @ 2008-01-01 2:22 UTC (permalink / raw)
To: netdev; +Cc: Jay Cliburn
Move some stray defines out to a header file. Improve indentation from
ghastly to horrid.
Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net>
---
drivers/net/atlx/atl1.c | 29 ++++++++++++-----------------
drivers/net/atlx/atl1.h | 6 ++++++
2 files changed, 18 insertions(+), 17 deletions(-)
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index 9c86ef4..f40cc6e 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -217,12 +217,6 @@ static s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
return ATLX_ERR_PHY;
}
-#define CUSTOM_SPI_CS_SETUP 2
-#define CUSTOM_SPI_CLK_HI 2
-#define CUSTOM_SPI_CLK_LO 2
-#define CUSTOM_SPI_CS_HOLD 2
-#define CUSTOM_SPI_CS_HI 3
-
static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
{
int i;
@@ -232,17 +226,18 @@ static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
value = SPI_FLASH_CTRL_WAIT_READY |
- (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
- SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
- SPI_FLASH_CTRL_CLK_HI_MASK) <<
- SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
- SPI_FLASH_CTRL_CLK_LO_MASK) <<
- SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
- SPI_FLASH_CTRL_CS_HOLD_MASK) <<
- SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
- SPI_FLASH_CTRL_CS_HI_MASK) <<
- SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
- SPI_FLASH_CTRL_INS_SHIFT;
+ (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
+ SPI_FLASH_CTRL_CS_SETUP_SHIFT |
+ (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) <<
+ SPI_FLASH_CTRL_CLK_HI_SHIFT |
+ (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) <<
+ SPI_FLASH_CTRL_CLK_LO_SHIFT |
+ (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) <<
+ SPI_FLASH_CTRL_CS_HOLD_SHIFT |
+ (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) <<
+ SPI_FLASH_CTRL_CS_HI_SHIFT |
+ (1 & SPI_FLASH_CTRL_INS_MASK) <<
+ SPI_FLASH_CTRL_INS_SHIFT;
iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
diff --git a/drivers/net/atlx/atl1.h b/drivers/net/atlx/atl1.h
index 8198f82..3db9a34 100644
--- a/drivers/net/atlx/atl1.h
+++ b/drivers/net/atlx/atl1.h
@@ -335,6 +335,12 @@ extern const struct ethtool_ops atl1_ethtool_ops;
#define ATL1_EEDUMP_LEN 48
+#define CUSTOM_SPI_CS_SETUP 2
+#define CUSTOM_SPI_CLK_HI 2
+#define CUSTOM_SPI_CLK_LO 2
+#define CUSTOM_SPI_CS_HOLD 2
+#define CUSTOM_SPI_CS_HI 3
+
/* Statistics counters collected by the MAC */
struct stats_msg_block {
/* rx */
--
1.5.3.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 15/26] atl1: tidy up ring management
2008-01-01 2:22 [PATCH 00/26] atl1: divide and modernize Jay Cliburn
` (13 preceding siblings ...)
2008-01-01 2:22 ` [PATCH 14/26] atl1: move stray defines to header file Jay Cliburn
@ 2008-01-01 2:22 ` Jay Cliburn
2008-01-01 2:22 ` [PATCH 16/26] atl1: modernize check link function Jay Cliburn
` (11 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Jay Cliburn @ 2008-01-01 2:22 UTC (permalink / raw)
To: netdev; +Cc: Jay Cliburn
Check for null pointers and such in ring handling functions. Make
needlessly global functions static. Clean up some comments and indentation.
Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net>
---
drivers/net/atlx/atl1.c | 20 +++++++++++---------
1 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index f40cc6e..db6e76c 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -141,8 +141,7 @@ static s32 atl1_reset_hw(struct atl1_hw *hw)
return 0;
}
-/* function about EEPROM
- *
+/*
* check_eeprom_exist
* return 0 if eeprom exist
*/
@@ -166,7 +165,7 @@ static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
u32 control;
if (offset & 3)
- /* address do not align */
+ /* unaligned address */
return false;
iowrite32(0, hw->hw_addr + REG_VPD_DATA);
@@ -417,7 +416,7 @@ static void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
* bit BitArray[hash_value]. So we figure out what register
* the bit is in, read it, OR in the new bit, then write
* back the new value. The register is determined by the
- * upper 7 bits of the hash value and the bit within that
+ * upper bit of the hash value, and the bits within that
* register are determined by the lower 5 bits of the value.
*/
hash_reg = (hash_value >> 31) & 0x1;
@@ -439,9 +438,9 @@ static s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
u32 val;
val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
- (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
- MDIO_SUP_PREAMBLE |
- MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
+ (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
+ MDIO_SUP_PREAMBLE | MDIO_START |
+ MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
ioread32(hw->hw_addr + REG_MDIO_CTRL);
@@ -872,7 +871,7 @@ static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
*
* Return 0 on success, negative on failure
*/
-s32 atl1_setup_ring_resources(struct atl1_adapter *adapter)
+static s32 atl1_setup_ring_resources(struct atl1_adapter *adapter)
{
struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
@@ -987,6 +986,9 @@ static void atl1_clean_rx_ring(struct atl1_adapter *adapter)
unsigned long size;
unsigned int i;
+ if (!rfd_ring->buffer_info || !rfd_ring->desc)
+ return;
+
/* Free all the Rx ring sk_buffs */
for (i = 0; i < rfd_ring->count; i++) {
buffer_info = &rfd_ring->buffer_info[i];
@@ -1060,7 +1062,7 @@ static void atl1_clean_tx_ring(struct atl1_adapter *adapter)
*
* Free all transmit software resources
*/
-void atl1_free_ring_resources(struct atl1_adapter *adapter)
+static void atl1_free_ring_resources(struct atl1_adapter *adapter)
{
struct pci_dev *pdev = adapter->pdev;
struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
--
1.5.3.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 16/26] atl1: modernize check link function
2008-01-01 2:22 [PATCH 00/26] atl1: divide and modernize Jay Cliburn
` (14 preceding siblings ...)
2008-01-01 2:22 ` [PATCH 15/26] atl1: tidy up ring management Jay Cliburn
@ 2008-01-01 2:22 ` Jay Cliburn
2008-01-01 2:22 ` [PATCH 17/26] atl1: update phy config function Jay Cliburn
` (10 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Jay Cliburn @ 2008-01-01 2:22 UTC (permalink / raw)
To: netdev; +Cc: Jay Cliburn
Update atl1_check_link() to conform with the current vendor driver version
1.2.40.2. Clean up vertical spacing, indentation, and remove dead code.
Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net>
---
drivers/net/atlx/atl1.c | 65 +++++++++++++++-------------------------------
drivers/net/atlx/atl1.h | 1 +
2 files changed, 22 insertions(+), 44 deletions(-)
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index db6e76c..abed547 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -1094,6 +1094,7 @@ static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter)
u32 value;
struct atl1_hw *hw = &adapter->hw;
struct net_device *netdev = adapter->netdev;
+
/* Config MAC CTRL Register */
value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
/* duplex */
@@ -1101,8 +1102,8 @@ static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter)
value |= MAC_CTRL_DUPLX;
/* speed */
value |= ((u32) ((SPEED_1000 == adapter->link_speed) ?
- MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
- MAC_CTRL_SPEED_SHIFT);
+ MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
+ MAC_CTRL_SPEED_SHIFT);
/* flow control */
value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
/* PAD & CRC */
@@ -1113,10 +1114,6 @@ static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter)
/* vlan */
if (adapter->vlgrp)
value |= MAC_CTRL_RMV_VLAN;
- /* rx checksum
- if (adapter->rx_csum)
- value |= MAC_CTRL_RX_CHKSUM_EN;
- */
/* filter mode */
value |= MAC_CTRL_BC_EN;
if (netdev->flags & IFF_PROMISC)
@@ -1131,7 +1128,7 @@ static u32 atl1_check_link(struct atl1_adapter *adapter)
{
struct atl1_hw *hw = &adapter->hw;
struct net_device *netdev = adapter->netdev;
- u32 ret_val;
+ u32 val, retval;
u16 speed, duplex, phy_data;
int reconfig = 0;
@@ -1143,6 +1140,10 @@ static u32 atl1_check_link(struct atl1_adapter *adapter)
if (netif_carrier_ok(netdev)) {
/* old link state: Up */
dev_info(&adapter->pdev->dev, "link is down\n");
+ val = ioread32(hw->hw_addr + REG_MAC_CTRL);
+ val &= ~MAC_CTRL_RX_EN;
+ iowrite32(val, hw->hw_addr + REG_MAC_CTRL);
+ ioread32(hw->hw_addr + REG_MAC_CTRL);
adapter->link_speed = SPEED_0;
netif_carrier_off(netdev);
netif_stop_queue(netdev);
@@ -1151,15 +1152,12 @@ static u32 atl1_check_link(struct atl1_adapter *adapter)
}
/* Link Up */
- ret_val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
- if (ret_val)
- return ret_val;
+ retval = atl1_get_speed_and_duplex(hw, &speed, &duplex);
+ clear_bit(0, &hw->force_ps);
+ if (retval)
+ return retval;
switch (hw->media_type) {
- case MEDIA_TYPE_1000M_FULL:
- if (speed != SPEED_1000 || duplex != FULL_DUPLEX)
- reconfig = 1;
- break;
case MEDIA_TYPE_100M_FULL:
if (speed != SPEED_100 || duplex != FULL_DUPLEX)
reconfig = 1;
@@ -1180,8 +1178,8 @@ static u32 atl1_check_link(struct atl1_adapter *adapter)
/* link result is our setting */
if (!reconfig) {
- if (adapter->link_speed != speed
- || adapter->link_duplex != duplex) {
+ if (adapter->link_speed != speed ||
+ adapter->link_duplex != duplex) {
adapter->link_speed = speed;
adapter->link_duplex = duplex;
atl1_setup_mac_ctrl(adapter);
@@ -1201,39 +1199,18 @@ static u32 atl1_check_link(struct atl1_adapter *adapter)
/* change original link status */
if (netif_carrier_ok(netdev)) {
+ val = ioread32(hw->hw_addr + REG_MAC_CTRL);
+ val &= ~MAC_CTRL_RX_EN;
adapter->link_speed = SPEED_0;
+ iowrite32(val, hw->hw_addr + REG_MAC_CTRL);
+ ioread32(hw->hw_addr + REG_MAC_CTRL);
netif_carrier_off(netdev);
netif_stop_queue(netdev);
}
- if (hw->media_type != MEDIA_TYPE_AUTO_SENSOR &&
- hw->media_type != MEDIA_TYPE_1000M_FULL) {
- switch (hw->media_type) {
- case MEDIA_TYPE_100M_FULL:
- phy_data = MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
- MII_CR_RESET;
- break;
- case MEDIA_TYPE_100M_HALF:
- phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
- break;
- case MEDIA_TYPE_10M_FULL:
- phy_data =
- MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
- break;
- default:
- /* MEDIA_TYPE_10M_HALF: */
- phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
- break;
- }
- atl1_write_phy_reg(hw, MII_BMCR, phy_data);
- return 0;
- }
-
- /* auto-neg, insert timer to re-config phy */
- if (!adapter->phy_timer_pending) {
- adapter->phy_timer_pending = true;
- mod_timer(&adapter->phy_config_timer, jiffies + 3 * HZ);
- }
+ /* autoneg, insert timer to reconfig phy */
+ if (!test_and_set_bit(0, &adapter->cfg_phy))
+ mod_timer(&adapter->phy_config_timer, jiffies + 5 * HZ);
return 0;
}
diff --git a/drivers/net/atlx/atl1.h b/drivers/net/atlx/atl1.h
index 3db9a34..1f245e0 100644
--- a/drivers/net/atlx/atl1.h
+++ b/drivers/net/atlx/atl1.h
@@ -791,6 +791,7 @@ struct atl1_adapter {
struct timer_list watchdog_timer;
struct timer_list phy_config_timer;
bool phy_timer_pending;
+ unsigned long cfg_phy;
/* all descriptor rings' memory */
struct atl1_ring_header ring_header;
--
1.5.3.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 17/26] atl1: update phy config function
2008-01-01 2:22 [PATCH 00/26] atl1: divide and modernize Jay Cliburn
` (15 preceding siblings ...)
2008-01-01 2:22 ` [PATCH 16/26] atl1: modernize check link function Jay Cliburn
@ 2008-01-01 2:22 ` Jay Cliburn
2008-01-01 2:22 ` [PATCH 18/26] atl1: make function static Jay Cliburn
` (9 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Jay Cliburn @ 2008-01-01 2:22 UTC (permalink / raw)
To: netdev; +Cc: Jay Cliburn
Update atl1_phy_config() to conform with current vendor driver version
1.2.40.2.
Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net>
---
drivers/net/atlx/atl1.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index abed547..6432956 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -2344,11 +2344,11 @@ static void atl1_phy_config(unsigned long data)
unsigned long flags;
spin_lock_irqsave(&adapter->lock, flags);
- adapter->phy_timer_pending = false;
atl1_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
atl1_write_phy_reg(hw, MII_ATLX_CR, hw->mii_1000t_ctrl_reg);
atl1_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN);
spin_unlock_irqrestore(&adapter->lock, flags);
+ clear_bit(0, &adapter->cfg_phy);
}
int atl1_reset(struct atl1_adapter *adapter)
--
1.5.3.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 18/26] atl1: make function static
2008-01-01 2:22 [PATCH 00/26] atl1: divide and modernize Jay Cliburn
` (16 preceding siblings ...)
2008-01-01 2:22 ` [PATCH 17/26] atl1: update phy config function Jay Cliburn
@ 2008-01-01 2:22 ` Jay Cliburn
2008-01-01 2:22 ` [PATCH 19/26] atl1: modernize down/up functions Jay Cliburn
` (8 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Jay Cliburn @ 2008-01-01 2:22 UTC (permalink / raw)
To: netdev; +Cc: Jay Cliburn
Make atl1_reset() a static function.
Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net>
---
drivers/net/atlx/atl1.c | 11 ++++++-----
1 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index 6432956..7697e80 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -2351,12 +2351,13 @@ static void atl1_phy_config(unsigned long data)
clear_bit(0, &adapter->cfg_phy);
}
-int atl1_reset(struct atl1_adapter *adapter)
+static int atl1_reset(struct atl1_adapter *adapter)
{
- int ret;
- ret = atl1_reset_hw(&adapter->hw);
- if (ret)
- return ret;
+ int retval;
+
+ retval = atl1_reset_hw(&adapter->hw);
+ if (retval)
+ return retval;
return atl1_init_hw(&adapter->hw);
}
--
1.5.3.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 19/26] atl1: modernize down/up functions
2008-01-01 2:22 [PATCH 00/26] atl1: divide and modernize Jay Cliburn
` (17 preceding siblings ...)
2008-01-01 2:22 ` [PATCH 18/26] atl1: make function static Jay Cliburn
@ 2008-01-01 2:22 ` Jay Cliburn
2008-01-01 2:22 ` [PATCH 20/26] atl1: update change mtu Jay Cliburn
` (7 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Jay Cliburn @ 2008-01-01 2:22 UTC (permalink / raw)
To: netdev; +Cc: Jay Cliburn
Update atl1_down() and atl1_up() to conform with the current vendor driver
version 1.2.40.2.
Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net>
---
drivers/net/atlx/atl1.c | 21 ++++++++-------------
drivers/net/atlx/atl1.h | 1 -
drivers/net/atlx/atlx.c | 2 +-
3 files changed, 9 insertions(+), 15 deletions(-)
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index 7697e80..972de34 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -2388,7 +2388,6 @@ static s32 atl1_up(struct atl1_adapter *adapter)
}
clear_bit(__ATL1_DOWN, &adapter->flags);
- mod_timer(&adapter->watchdog_timer, jiffies + (4 * HZ));
retval = ioread32(&adapter->hw + REG_MASTER_CTRL);
retval |= MASTER_CTRL_MANUAL_INT;
iowrite32(retval, &adapter->hw + REG_MASTER_CTRL);
@@ -2401,21 +2400,18 @@ void atl1_down(struct atl1_adapter *adapter)
{
struct net_device *netdev = adapter->netdev;
- del_timer_sync(&adapter->watchdog_timer);
- del_timer_sync(&adapter->phy_config_timer);
- adapter->phy_timer_pending = false;
-
- atlx_irq_disable(adapter);
- free_irq(adapter->pdev->irq, netdev);
- pci_disable_msi(adapter->pdev);
+ set_bit(__ATL1_DOWN, &adapter->flags);
+ netif_stop_queue(netdev);
atl1_reset_hw(&adapter->hw);
adapter->cmb.cmb->int_stats = 0;
-
+ msleep(1);
+ atlx_irq_disable(adapter);
+ del_timer_sync(&adapter->watchdog_timer);
+ del_timer_sync(&adapter->phy_config_timer);
+ clear_bit(0, &adapter->cfg_phy);
+ netif_carrier_off(netdev);
adapter->link_speed = SPEED_0;
adapter->link_duplex = -1;
- netif_carrier_off(netdev);
- netif_stop_queue(netdev);
-
atl1_clean_tx_ring(adapter);
atl1_clean_rx_ring(adapter);
}
@@ -2821,7 +2817,6 @@ static int __devinit atl1_probe(struct pci_dev *pdev,
init_timer(&adapter->phy_config_timer);
adapter->phy_config_timer.function = &atl1_phy_config;
adapter->phy_config_timer.data = (unsigned long)adapter;
- adapter->phy_timer_pending = false;
INIT_WORK(&adapter->reset_task, atl1_reset_task);
INIT_WORK(&adapter->link_chg_task, atlx_link_chg_task);
diff --git a/drivers/net/atlx/atl1.h b/drivers/net/atlx/atl1.h
index 1f245e0..5187f74 100644
--- a/drivers/net/atlx/atl1.h
+++ b/drivers/net/atlx/atl1.h
@@ -790,7 +790,6 @@ struct atl1_adapter {
struct work_struct link_chg_task;
struct timer_list watchdog_timer;
struct timer_list phy_config_timer;
- bool phy_timer_pending;
unsigned long cfg_phy;
/* all descriptor rings' memory */
diff --git a/drivers/net/atlx/atlx.c b/drivers/net/atlx/atlx.c
index 18c2d7e..9cc9441 100644
--- a/drivers/net/atlx/atlx.c
+++ b/drivers/net/atlx/atlx.c
@@ -91,7 +91,6 @@ static void atlx_check_for_link(struct atlx_adapter *adapter)
u16 phy_data = 0;
spin_lock(&adapter->lock);
- adapter->phy_timer_pending = false;
atlx_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
atlx_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
spin_unlock(&adapter->lock);
@@ -104,6 +103,7 @@ static void atlx_check_for_link(struct atlx_adapter *adapter)
dev_info(&adapter->pdev->dev, "%s link is down\n",
netdev->name);
adapter->link_speed = SPEED_0;
+ clear_bit(0, &adapter->hw.force_ps);
netif_carrier_off(netdev);
netif_stop_queue(netdev);
}
--
1.5.3.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 20/26] atl1: update change mtu
2008-01-01 2:22 [PATCH 00/26] atl1: divide and modernize Jay Cliburn
` (18 preceding siblings ...)
2008-01-01 2:22 ` [PATCH 19/26] atl1: modernize down/up functions Jay Cliburn
@ 2008-01-01 2:22 ` Jay Cliburn
2008-01-01 2:22 ` [PATCH 21/26] atl1: update atl1_close Jay Cliburn
` (6 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Jay Cliburn @ 2008-01-01 2:22 UTC (permalink / raw)
To: netdev; +Cc: Jay Cliburn
Update atl1_change_mtu() to conform with the current vendor driver version
1.2.40.2.
Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net>
---
drivers/net/atlx/atl1.c | 39 ++++++++++++++++++++++-----------------
1 files changed, 22 insertions(+), 17 deletions(-)
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index 972de34..7d84a51 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -2438,32 +2438,37 @@ static void atl1_reset_task(struct work_struct *work)
* atl1_change_mtu - Change the Maximum Transfer Unit
* @netdev: network interface device structure
* @new_mtu: new value for maximum frame size
- *
- * Returns 0 on success, negative on failure
*/
static int atl1_change_mtu(struct net_device *netdev, int new_mtu)
{
struct atl1_adapter *adapter = netdev_priv(netdev);
- int old_mtu = netdev->mtu;
- int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
+ struct atl1_hw *hw = &adapter->hw;
- if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
- (max_frame > MAX_JUMBO_FRAME_SIZE)) {
- dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
+ if ((new_mtu < 40) || (new_mtu > (ETH_DATA_LEN + VLAN_HLEN)))
return -EINVAL;
- }
- adapter->hw.max_frame_size = max_frame;
- adapter->hw.tx_jumbo_task_th = (max_frame + 7) >> 3;
- adapter->rx_buffer_len = (max_frame + 7) & ~7;
- adapter->hw.rx_jumbo_th = adapter->rx_buffer_len / 8;
+ if (hw->max_frame_size != new_mtu) {
+ while (test_and_set_bit(__ATL1_RESETTING, &adapter->flags))
+ msleep(1);
- netdev->mtu = new_mtu;
- if ((old_mtu != new_mtu) && netif_running(netdev)) {
- atl1_down(adapter);
- atl1_up(adapter);
- }
+ if (netif_running(netdev))
+ atl1_down(adapter);
+
+ netdev->mtu = new_mtu;
+ adapter->hw.max_frame_size = new_mtu;
+ adapter->hw.tx_jumbo_task_th = (new_mtu + ETH_HLEN +
+ ETH_FCS_LEN + VLAN_HLEN + 7) >> 3;
+ adapter->rx_buffer_len = (new_mtu + ETH_HLEN +
+ ETH_FCS_LEN + VLAN_HLEN + 7) & ~7;
+ adapter->hw.rx_jumbo_th = adapter->rx_buffer_len / 8;
+ if (netif_running(netdev))
+ atl1_up(adapter);
+ else
+ atl1_reset(adapter);
+
+ clear_bit(__ATL1_RESETTING, &adapter->flags);
+ }
return 0;
}
--
1.5.3.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 21/26] atl1: update atl1_close
2008-01-01 2:22 [PATCH 00/26] atl1: divide and modernize Jay Cliburn
` (19 preceding siblings ...)
2008-01-01 2:22 ` [PATCH 20/26] atl1: update change mtu Jay Cliburn
@ 2008-01-01 2:22 ` Jay Cliburn
2008-01-01 2:22 ` [PATCH 22/26] atl1: update netpoll Jay Cliburn
` (5 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Jay Cliburn @ 2008-01-01 2:22 UTC (permalink / raw)
To: netdev; +Cc: Jay Cliburn
Update atl1_close() to conform with current vendor driver version 1.2.40.2.
Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net>
---
drivers/net/atlx/atl1.c | 14 ++++++++++++++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index 7d84a51..997c83c 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -2558,6 +2558,18 @@ err_open:
return err;
}
+static void atl1_free_irq(struct atl1_adapter *adapter)
+{
+ struct net_device *netdev = adapter->netdev;
+
+ free_irq(adapter->pdev->irq, netdev);
+
+#ifdef CONFIG_PCI_MSI
+ if (adapter->have_msi)
+ pci_disable_msi(adapter->pdev);
+#endif
+}
+
/*
* atl1_close - Disables a network interface
* @netdev: network interface device structure
@@ -2572,7 +2584,9 @@ err_open:
static int atl1_close(struct net_device *netdev)
{
struct atl1_adapter *adapter = netdev_priv(netdev);
+
atl1_down(adapter);
+ atl1_free_irq(adapter);
atl1_free_ring_resources(adapter);
return 0;
}
--
1.5.3.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 22/26] atl1: update netpoll
2008-01-01 2:22 [PATCH 00/26] atl1: divide and modernize Jay Cliburn
` (20 preceding siblings ...)
2008-01-01 2:22 ` [PATCH 21/26] atl1: update atl1_close Jay Cliburn
@ 2008-01-01 2:22 ` Jay Cliburn
2008-01-01 2:22 ` [PATCH 23/26] atl1: update shutdown and remove functions Jay Cliburn
` (4 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Jay Cliburn @ 2008-01-01 2:22 UTC (permalink / raw)
To: netdev; +Cc: Jay Cliburn
Rename atl1_poll_controller() to atl1_netpoll() and update to conform with
the current vendor driver version 1.2.40.2.
Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net>
---
drivers/net/atlx/atl1.c | 11 +++++++----
1 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index 997c83c..f09928d 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -2691,11 +2691,14 @@ static int atl1_resume(struct pci_dev *pdev)
#endif
#ifdef CONFIG_NET_POLL_CONTROLLER
-static void atl1_poll_controller(struct net_device *netdev)
+static void atl1_netpoll(struct net_device *netdev)
{
- disable_irq(netdev->irq);
+ struct atl1_adapter *adapter = netdev_priv(netdev);
+
+ disable_irq(adapter->pdev->irq);
atl1_intr(netdev->irq, netdev);
- enable_irq(netdev->irq);
+ atl1_clean_tx_irq(adapter);
+ enable_irq(adapter->pdev->irq);
}
#endif
@@ -2796,7 +2799,7 @@ static int __devinit atl1_probe(struct pci_dev *pdev,
netdev->tx_timeout = &atlx_tx_timeout;
netdev->watchdog_timeo = 5 * HZ;
#ifdef CONFIG_NET_POLL_CONTROLLER
- netdev->poll_controller = atl1_poll_controller;
+ netdev->poll_controller = atl1_netpoll;
#endif
netdev->vlan_rx_register = atlx_vlan_rx_register;
--
1.5.3.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 23/26] atl1: update shutdown and remove functions
2008-01-01 2:22 [PATCH 00/26] atl1: divide and modernize Jay Cliburn
` (21 preceding siblings ...)
2008-01-01 2:22 ` [PATCH 22/26] atl1: update netpoll Jay Cliburn
@ 2008-01-01 2:22 ` Jay Cliburn
2008-01-01 2:22 ` [PATCH 24/26] atl1: update wake-on-lan Jay Cliburn
` (3 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Jay Cliburn @ 2008-01-01 2:22 UTC (permalink / raw)
To: netdev; +Cc: Jay Cliburn
Update shutdown and remove functions to conform with the current vendor
driver version 1.2.40.2.
Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net>
---
drivers/net/atlx/atl1.c | 31 +++++++++++++++++++++++--------
1 files changed, 23 insertions(+), 8 deletions(-)
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index f09928d..b89201e 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -2591,6 +2591,16 @@ static int atl1_close(struct net_device *netdev)
return 0;
}
+static void atl1_force_ps(struct atl1_hw *hw)
+{
+ atl1_write_phy_reg(hw, MII_DBG_ADDR, 0);
+ atl1_write_phy_reg(hw, MII_DBG_DATA, 0x124E);
+ atl1_write_phy_reg(hw, MII_DBG_ADDR, 2);
+ atl1_write_phy_reg(hw, MII_DBG_DATA, 0x3000);
+ atl1_write_phy_reg(hw, MII_DBG_ADDR, 3);
+ atl1_write_phy_reg(hw, MII_DBG_DATA, 0);
+}
+
#ifdef CONFIG_PM
static int atl1_suspend(struct pci_dev *pdev, pm_message_t state)
{
@@ -2878,12 +2888,7 @@ err_request_regions:
static void __devexit atl1_remove(struct pci_dev *pdev)
{
struct net_device *netdev = pci_get_drvdata(pdev);
- struct atl1_adapter *adapter;
- /* Device not available. Return. */
- if (!netdev)
- return;
-
- adapter = netdev_priv(netdev);
+ struct atl1_adapter *adapter = netdev_priv(netdev);
/*
* Some atl1 boards lack persistent storage for their MAC, and get it
@@ -2896,21 +2901,31 @@ static void __devexit atl1_remove(struct pci_dev *pdev)
atl1_set_mac_addr(&adapter->hw);
}
- iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
+ set_bit(__ATL1_DOWN, &adapter->flags);
+ del_timer_sync(&adapter->watchdog_timer);
+ del_timer_sync(&adapter->phy_config_timer);
+ flush_scheduled_work();
unregister_netdev(netdev);
+ atl1_force_ps(&adapter->hw);
pci_iounmap(pdev, adapter->hw.hw_addr);
pci_release_regions(pdev);
free_netdev(netdev);
pci_disable_device(pdev);
}
+static void atl1_shutdown(struct pci_dev *pdev)
+{
+ atl1_suspend(pdev, PMSG_SUSPEND);
+}
+
static struct pci_driver atl1_driver = {
.name = ATLX_DRIVER_NAME,
.id_table = atl1_pci_tbl,
.probe = atl1_probe,
.remove = __devexit_p(atl1_remove),
.suspend = atl1_suspend,
- .resume = atl1_resume
+ .resume = atl1_resume,
+ .shutdown = atl1_shutdown
};
/*
--
1.5.3.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 24/26] atl1: update wake-on-lan
2008-01-01 2:22 [PATCH 00/26] atl1: divide and modernize Jay Cliburn
` (22 preceding siblings ...)
2008-01-01 2:22 ` [PATCH 23/26] atl1: update shutdown and remove functions Jay Cliburn
@ 2008-01-01 2:22 ` Jay Cliburn
2008-01-01 2:22 ` [PATCH 25/26] atl1: add NAPI support Jay Cliburn
` (2 subsequent siblings)
26 siblings, 0 replies; 30+ messages in thread
From: Jay Cliburn @ 2008-01-01 2:22 UTC (permalink / raw)
To: netdev; +Cc: Jay Cliburn
Update wake-on-lan to conform with the current vendor driver version
1.2.40.2.
Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net>
---
drivers/net/atlx/atl1.c | 140 ++++++++++++++++++++++++++++-------------------
1 files changed, 84 insertions(+), 56 deletions(-)
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index b89201e..237622e 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -1457,22 +1457,6 @@ static u32 atl1_configure(struct atl1_adapter *adapter)
return value;
}
-/*
- * When ACPI resume on some VIA MotherBoard, the Interrupt Disable bit/0x400
- * on PCI Command register is disable.
- * The function enable this bit.
- * Brackett, 2006/03/15
- */
-static void atl1_via_workaround(struct atl1_adapter *adapter)
-{
- unsigned long value;
-
- value = ioread16(adapter->hw.hw_addr + PCI_COMMAND);
- if (value & PCI_COMMAND_INTX_DISABLE)
- value &= ~PCI_COMMAND_INTX_DISABLE;
- iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND);
-}
-
static void atl1_inc_smb(struct atl1_adapter *adapter)
{
struct stats_msg_block *smb = adapter->smb.smb;
@@ -2607,65 +2591,97 @@ static int atl1_suspend(struct pci_dev *pdev, pm_message_t state)
struct net_device *netdev = pci_get_drvdata(pdev);
struct atl1_adapter *adapter = netdev_priv(netdev);
struct atl1_hw *hw = &adapter->hw;
+ u16 speed, duplex;
u32 ctrl = 0;
u32 wufc = adapter->wol;
+ int retval;
netif_device_detach(netdev);
- if (netif_running(netdev))
+ if (netif_running(netdev)) {
+ WARN_ON(test_bit(__ATL1_RESETTING, &adapter->flags));
atl1_down(adapter);
+ }
+
+ retval = pci_save_state(pdev);
+ if (retval)
+ return retval;
- atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
- atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
+ atl1_read_phy_reg(hw, MII_BMSR, (u16 *) &ctrl);
+ atl1_read_phy_reg(hw, MII_BMSR, (u16 *) &ctrl);
if (ctrl & BMSR_LSTATUS)
wufc &= ~ATLX_WUFC_LNKC;
- /* reduce speed to 10/100M */
- if (wufc) {
- /* if resume, let driver to re- setup link */
- hw->phy_configured = false;
- atl1_set_mac_addr(hw);
- atlx_set_multi(netdev);
+ if ((ctrl & BMSR_LSTATUS) && wufc) {
+ retval = atl1_get_speed_and_duplex(hw, &speed, &duplex);
+ if (retval) {
+ dev_printk(KERN_DEBUG, &adapter->pdev->dev,
+ "speed/duplex error during suspend\n");
+ goto wol_dis;
+ }
ctrl = 0;
/* turn on magic packet wol */
if (wufc & ATLX_WUFC_MAG)
ctrl = WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
- /* turn on Link change WOL */
- if (wufc & ATLX_WUFC_LNKC)
- ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
- /* turn on all-multi mode if wake on multicast is enabled */
- ctrl = ioread32(hw->hw_addr + REG_MAC_CTRL);
- ctrl &= ~MAC_CTRL_DBG;
- ctrl &= ~MAC_CTRL_PROMIS_EN;
- if (wufc & ATLX_WUFC_MC)
- ctrl |= MAC_CTRL_MC_ALL_EN;
- else
- ctrl &= ~MAC_CTRL_MC_ALL_EN;
+ ctrl = MAC_CTRL_RX_EN;
+ ctrl |= ((u32) ((speed == SPEED_1000) ? MAC_CTRL_SPEED_1000 :
+ MAC_CTRL_SPEED_10_100) << MAC_CTRL_SPEED_SHIFT);
+
+ if (duplex == FULL_DUPLEX)
+ ctrl |= (((u32) adapter->hw.preamble_len &
+ MAC_CTRL_PRMLEN_MASK) <<
+ MAC_CTRL_PRMLEN_SHIFT);
- /* turn on broadcast mode if wake on-BC is enabled */
- if (wufc & ATLX_WUFC_BC)
+ if (adapter->vlgrp)
+ ctrl |= MAC_CTRL_RMV_VLAN;
+
+ if (wufc & ATLX_WUFC_MAG)
ctrl |= MAC_CTRL_BC_EN;
- else
- ctrl &= ~MAC_CTRL_BC_EN;
- /* enable RX */
- ctrl |= MAC_CTRL_RX_EN;
iowrite32(ctrl, hw->hw_addr + REG_MAC_CTRL);
- pci_enable_wake(pdev, PCI_D3hot, 1);
- pci_enable_wake(pdev, PCI_D3cold, 1);
- } else {
- iowrite32(0, hw->hw_addr + REG_WOL_CTRL);
- pci_enable_wake(pdev, PCI_D3hot, 0);
- pci_enable_wake(pdev, PCI_D3cold, 0);
+
+ ctrl = ioread32(hw->hw_addr + REG_PCIE_PHY_MISC1);
+ ctrl |= PCIE_PHY_MISC1_FORCE_RCV_DET;
+ iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHY_MISC1);
+ ioread32(hw->hw_addr + REG_PCIE_PHY_MISC1);
+ hw->phy_configured = false;
+ pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
+ goto suspend_exit;
}
- pci_save_state(pdev);
- pci_disable_device(pdev);
+ if (!(ctrl & BMSR_LSTATUS) && (wufc & ATLX_WUFC_LNKC)) {
+ ctrl |= WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN;
+ iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
+ iowrite32(0, hw->hw_addr + REG_MAC_CTRL);
+
+ ctrl = ioread32(hw->hw_addr + REG_PCIE_PHY_MISC1);
+ ctrl |= PCIE_PHY_MISC1_FORCE_RCV_DET;
+ iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHY_MISC1);
+ ioread32(hw->hw_addr + REG_PCIE_PHY_MISC1);
+ hw->phy_configured = false;
+ pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
+ goto suspend_exit;
+ }
+
+wol_dis:
+ iowrite32(0, hw->hw_addr + REG_WOL_CTRL);
+ ctrl = ioread32(hw->hw_addr + REG_PCIE_PHY_MISC1);
+ ctrl |= PCIE_PHY_MISC1_FORCE_RCV_DET;
+ iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHY_MISC1);
+ ioread32(hw->hw_addr + REG_PCIE_PHY_MISC1);
+ atl1_force_ps(hw);
+ hw->phy_configured = false;
+ pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
+
+suspend_exit:
+ if (netif_running(netdev))
+ atl1_free_irq(adapter);
- pci_set_power_state(pdev, PCI_D3hot);
+ pci_disable_device(pdev);
+ pci_set_power_state(pdev, pci_choose_state(pdev, state));
return 0;
}
@@ -2674,24 +2690,36 @@ static int atl1_resume(struct pci_dev *pdev)
{
struct net_device *netdev = pci_get_drvdata(pdev);
struct atl1_adapter *adapter = netdev_priv(netdev);
+ struct atl1_hw *hw = &adapter->hw;
u32 err;
pci_set_power_state(pdev, PCI_D0);
pci_restore_state(pdev);
- /* FIXME: check and handle */
err = pci_enable_device(pdev);
+ if (err) {
+ dev_printk(KERN_DEBUG, &adapter->pdev->dev,
+ "pci enable device error on resume\n");
+ return err;
+ }
+
+ pci_set_master(pdev);
+ ioread32(hw->hw_addr + REG_WOL_CTRL);
pci_enable_wake(pdev, PCI_D3hot, 0);
pci_enable_wake(pdev, PCI_D3cold, 0);
+ iowrite32(0, hw->hw_addr + REG_WOL_CTRL);
+
+ err = atl1_request_irq(adapter);
+ if (netif_running(netdev) && err)
+ return err;
- iowrite32(0, adapter->hw.hw_addr + REG_WOL_CTRL);
- atl1_reset(adapter);
+ atl1_reset_hw(hw);
+ adapter->cmb.cmb->int_stats = 0;
if (netif_running(netdev))
atl1_up(adapter);
- netif_device_attach(netdev);
- atl1_via_workaround(adapter);
+ netif_device_attach(netdev);
return 0;
}
--
1.5.3.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* [PATCH 25/26] atl1: add NAPI support
2008-01-01 2:22 [PATCH 00/26] atl1: divide and modernize Jay Cliburn
` (23 preceding siblings ...)
2008-01-01 2:22 ` [PATCH 24/26] atl1: update wake-on-lan Jay Cliburn
@ 2008-01-01 2:22 ` Jay Cliburn
2008-01-01 5:58 ` Stephen Hemminger
2008-01-01 2:22 ` [PATCH 26/26] atl1: remove experimental tag and clean up comments Jay Cliburn
2008-01-01 17:58 ` [PATCH 00/26] atl1: divide and modernize Christoph Hellwig
26 siblings, 1 reply; 30+ messages in thread
From: Jay Cliburn @ 2008-01-01 2:22 UTC (permalink / raw)
To: netdev; +Cc: Jay Cliburn
Add support for NAPI, styled after the e1000 NAPI implementation. That we
follow the e1000 for NAPI shouldn't come as much of a surprise, since the
entire atl1 driver is based heavily upon it.
Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net>
---
drivers/net/Kconfig | 14 ++++
drivers/net/atlx/atl1.c | 151 +++++++++++++++++++++++++++++++++++++++++++++--
drivers/net/atlx/atl1.h | 20 ++++++
drivers/net/atlx/atlx.h | 7 ++-
4 files changed, 186 insertions(+), 6 deletions(-)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index d9107e5..095629f 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2371,6 +2371,20 @@ config ATL1
To compile this driver as a module, choose M here. The module
will be called atl1.
+config ATL1_NAPI
+ bool "Use Rx Polling (NAPI) (EXPERIMENTAL)"
+ depends on ATL1 && EXPERIMENTAL
+ help
+ NAPI is a new driver API designed to reduce CPU and interrupt load
+ when the driver is receiving lots of packets from the card. It is
+ still somewhat experimental and thus not yet enabled by default.
+
+ If your estimated Rx load is 10kpps or more, or if the card will be
+ deployed on potentially unfriendly networks (e.g. in a firewall),
+ then say Y here.
+
+ If in doubt, say N.
+
endif # NETDEV_1000
#
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index 237622e..10bccf6 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -756,7 +756,16 @@ static void atl1_set_mac_addr(struct atl1_hw *hw)
static int atl1_alloc_queues(struct atl1_adapter *adapter)
{
- /* temporary placeholder function for NAPI */
+#ifdef CONFIG_ATL1_NAPI
+ int size;
+
+ size = sizeof(struct net_device) * adapter->num_rx_queues;
+ adapter->polling_netdev = kmalloc(size, GFP_KERNEL);
+ if (!adapter->polling_netdev)
+ return -ENOMEM;
+
+ memset(adapter->polling_netdev, 0, size);
+#endif
return 0;
}
@@ -770,6 +779,9 @@ static int __devinit atl1_sw_init(struct atl1_adapter *adapter)
struct atl1_hw *hw = &adapter->hw;
struct net_device *netdev = adapter->netdev;
int err;
+#ifdef CONFIG_ATL1_NAPI
+ int i;
+#endif
hw->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
hw->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
@@ -818,6 +830,14 @@ static int __devinit atl1_sw_init(struct atl1_adapter *adapter)
return -ENOMEM;
}
+#ifdef CONFIG_ATL1_NAPI
+ for (i = 0; i < adapter->num_rx_queues; i++) {
+ adapter->polling_netdev[i].priv = adapter;
+ dev_hold(&adapter->polling_netdev[i]);
+ set_bit(__LINK_STATE_START, &adapter->polling_netdev[i].state);
+ }
+#endif
+
spin_lock_init(&adapter->lock);
spin_lock_init(&adapter->mb_lock);
set_bit(__ATL1_DOWN, &adapter->flags);
@@ -1698,7 +1718,12 @@ next:
return num_alloc;
}
+#ifdef CONFIG_ATL1_NAPI
+static void atl1_clean_rx_irq(struct atl1_adapter *adapter, int *work_done,
+ int work_to_do)
+#else
static void atl1_clean_rx_irq(struct atl1_adapter *adapter)
+#endif
{
struct net_device *netdev = adapter->netdev;
int i, count;
@@ -1768,6 +1793,11 @@ chk_rrd:
break;
}
rrd_ok:
+#ifdef CONFIG_ATL1_NAPI
+ if (*work_done >= work_to_do)
+ break;
+ (*work_done)++;
+#endif
/* clean alloc flag for bad rrd */
atl1_clean_alloc_flag(adapter, rrd, 0);
@@ -1808,6 +1838,16 @@ rrd_ok:
atl1_rx_checksum(adapter, rrd, skb);
skb->protocol = eth_type_trans(skb, adapter->netdev);
+#ifdef CONFIG_ATL1_NAPI
+ if (adapter->vlgrp && (rrd->pkt_flg & PACKET_FLAG_VLAN_INS)) {
+ u16 vlan_tag = (rrd->vlan_tag >> 4) |
+ ((rrd->vlan_tag & 7) << 13) |
+ ((rrd->vlan_tag & 8) << 9);
+ vlan_hwaccel_receive_skb(skb, adapter->vlgrp, vlan_tag);
+ } else
+ netif_receive_skb(skb);
+
+#else
if (adapter->vlgrp && (rrd->pkt_flg & PACKET_FLAG_VLAN_INS)) {
u16 vlan_tag = (rrd->vlan_tag >> 4) |
((rrd->vlan_tag & 7) << 13) |
@@ -1815,6 +1855,7 @@ rrd_ok:
vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag);
} else
netif_rx(skb);
+#endif
/* let protocol layer free skb */
buffer_info->skb = NULL;
@@ -1837,6 +1878,9 @@ static bool atl1_clean_tx_irq(struct atl1_adapter *adapter)
struct atl1_buffer *buffer_info;
u16 sw_tpd_next_to_clean;
u16 cmb_tpd_next_to_clean;
+#ifdef CONFIG_ATL1_NAPI
+ unsigned int count = 0;
+#endif
sw_tpd_next_to_clean = atomic_read(&tpd_ring->next_to_clean);
cmb_tpd_next_to_clean = le16_to_cpu(adapter->cmb.cmb->tpd_cons_idx);
@@ -1859,6 +1903,10 @@ static bool atl1_clean_tx_irq(struct atl1_adapter *adapter)
if (++sw_tpd_next_to_clean == tpd_ring->count)
sw_tpd_next_to_clean = 0;
+#ifdef CONFIG_ATL1_NAPI
+ if (count++ == ATL1_NAPI_WEIGHT)
+ break;
+#endif
}
atomic_set(&tpd_ring->next_to_clean, sw_tpd_next_to_clean);
@@ -1872,6 +1920,40 @@ static bool atl1_clean_tx_irq(struct atl1_adapter *adapter)
return false;
}
+#ifdef CONFIG_ATL1_NAPI
+static int atl1_clean(struct napi_struct *napi, int budget)
+{
+ struct atl1_adapter *adapter = container_of(napi, struct atl1_adapter,
+ napi);
+ struct net_device *poll_dev = adapter->netdev;
+ int work_done = 0;
+ int tx_cleaned = 0;
+
+ adapter = poll_dev->priv;
+
+ if (!netif_carrier_ok(poll_dev))
+ goto quit_polling;
+
+ if (spin_trylock(&adapter->lock)) {
+ tx_cleaned = atl1_clean_tx_irq(adapter);
+ spin_unlock(&adapter->lock);
+ }
+
+ atl1_clean_rx_irq(adapter, &work_done, budget);
+
+ if ((!tx_cleaned && (work_done == 0)) ||
+ !netif_running(poll_dev)) {
+quit_polling:
+ netif_rx_complete(poll_dev, napi);
+
+ if (!test_bit(__ATL1_DOWN, &adapter->flags))
+ atlx_irq_enable(adapter);
+ }
+
+ return work_done;
+}
+#endif
+
static u16 atl1_tpd_avail(struct atl1_tpd_ring *tpd_ring)
{
u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
@@ -2175,7 +2257,6 @@ static int atl1_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
if (!spin_trylock_irqsave(&adapter->lock, flags)) {
/* Can't get lock - tell upper layer to requeue */
- dev_printk(KERN_DEBUG, &adapter->pdev->dev, "tx locked\n");
return NETDEV_TX_LOCKED;
}
@@ -2183,7 +2264,6 @@ static int atl1_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
/* not enough descriptors */
netif_stop_queue(netdev);
spin_unlock_irqrestore(&adapter->lock, flags);
- dev_printk(KERN_DEBUG, &adapter->pdev->dev, "tx busy\n");
return NETDEV_TX_BUSY;
}
@@ -2232,16 +2312,21 @@ static int atl1_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
*/
static irqreturn_t atl1_intr(int irq, void *data)
{
+ struct net_device *netdev = data;
struct atl1_adapter *adapter = netdev_priv(data);
struct atl1_hw *hw = &adapter->hw;
u32 status;
- int max_ints = 10;
+#ifndef CONFIG_ATL1_NAPI
+ int max_ints = 12;
+#endif
status = adapter->cmb.cmb->int_stats;
if (!status)
return IRQ_NONE;
+#ifndef CONFIG_ATL1_NAPI
loopint:
+#endif
/* clear CMB interrupt status at once */
adapter->cmb.cmb->int_stats = 0;
@@ -2256,7 +2341,7 @@ loopint:
if (status & ISR_PHY_LINKDOWN) {
dev_printk(KERN_DEBUG, &adapter->pdev->dev,
"pcie phy link down %x\n", status);
- if (netif_running(adapter->netdev)) {
+ if (netif_running(netdev)) {
/* reset MAC */
iowrite32(0, hw->hw_addr + REG_ISR);
iowrite32(0, hw->hw_addr + REG_IMR);
@@ -2292,6 +2377,24 @@ loopint:
if (status & ISR_TX_EVENT)
atl1_clean_tx_irq(adapter);
+#ifdef CONFIG_ATL1_NAPI
+ if (status & ISR_RX_EVENT) {
+ struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
+ struct rx_return_desc *rrd;
+ rrd = ATL1_RRD_DESC(rrd_ring,
+ ((u16) atomic_read(&rrd_ring->next_to_clean)));
+ if (rrd->xsz.valid) {
+ /* valid packet */
+ iowrite32(IMR_NONRX_MASK, hw->hw_addr + REG_IMR);
+ ioread32(hw->hw_addr + REG_IMR);
+
+ if (netif_rx_schedule_prep(netdev, &adapter->napi))
+ __netif_rx_schedule(netdev, &adapter->napi);
+ else
+ atlx_irq_enable(adapter);
+ }
+ }
+#else
/* rx event */
if (status & ISR_RX_EVENT)
atl1_clean_rx_irq(adapter);
@@ -2299,6 +2402,7 @@ loopint:
status = adapter->cmb.cmb->int_stats;
if ((--max_ints > 0) && status)
goto loopint;
+#endif
/* re-enable interrupts */
iowrite32((ISR_DIS_SMB | ISR_DIS_DMA), adapter->hw.hw_addr + REG_ISR);
@@ -2375,6 +2479,10 @@ static s32 atl1_up(struct atl1_adapter *adapter)
retval = ioread32(&adapter->hw + REG_MASTER_CTRL);
retval |= MASTER_CTRL_MANUAL_INT;
iowrite32(retval, &adapter->hw + REG_MASTER_CTRL);
+
+#ifdef CONFIG_ATL1_NAPI
+ napi_enable(&adapter->napi);
+#endif
atlx_irq_enable(adapter);
return 0;
@@ -2389,6 +2497,10 @@ void atl1_down(struct atl1_adapter *adapter)
atl1_reset_hw(&adapter->hw);
adapter->cmb.cmb->int_stats = 0;
msleep(1);
+
+#ifdef CONFIG_ATL1_NAPI
+ napi_disable(&adapter->napi);
+#endif
atlx_irq_disable(adapter);
del_timer_sync(&adapter->watchdog_timer);
del_timer_sync(&adapter->phy_config_timer);
@@ -2528,6 +2640,10 @@ static int atl1_open(struct net_device *netdev)
goto err_open;
clear_bit(__ATL1_DOWN, &adapter->flags);
+
+#ifdef CONFIG_ATL1_NAPI
+ napi_enable(&adapter->napi);
+#endif
mod_timer(&adapter->watchdog_timer, jiffies + (4 * HZ));
val = ioread32(hw->hw_addr + REG_MASTER_CTRL);
val |= MASTER_CTRL_MANUAL_INT;
@@ -2736,6 +2852,9 @@ static void atl1_netpoll(struct net_device *netdev)
disable_irq(adapter->pdev->irq);
atl1_intr(netdev->irq, netdev);
atl1_clean_tx_irq(adapter);
+#ifndef CONFIG_ATL1_NAPI
+ atl1_clean_rx_irq(adapter);
+#endif
enable_irq(adapter->pdev->irq);
}
#endif
@@ -2758,6 +2877,9 @@ static int __devinit atl1_probe(struct pci_dev *pdev,
struct atl1_adapter *adapter;
static int cards_found = 0;
int err;
+#ifdef CONFIG_ATL1_NAPI
+ int i;
+#endif
err = pci_enable_device(pdev);
if (err)
@@ -2836,6 +2958,9 @@ static int __devinit atl1_probe(struct pci_dev *pdev,
netdev->do_ioctl = &atlx_ioctl;
netdev->tx_timeout = &atlx_tx_timeout;
netdev->watchdog_timeo = 5 * HZ;
+#ifdef CONFIG_ATL1_NAPI
+ netif_napi_add(netdev, &adapter->napi, &atl1_clean, ATL1_NAPI_WEIGHT);
+#endif
#ifdef CONFIG_NET_POLL_CONTROLLER
netdev->poll_controller = atl1_netpoll;
#endif
@@ -2893,6 +3018,13 @@ static int __devinit atl1_probe(struct pci_dev *pdev,
return 0;
err_common:
+#ifdef CONFIG_ATL1_NAPI
+ if (adapter->polling_netdev) {
+ for (i = 0; i < adapter->num_rx_queues; i++)
+ dev_put(&adapter->polling_netdev[i]);
+ kfree(adapter->polling_netdev);
+ }
+#endif
pci_iounmap(pdev, adapter->hw.hw_addr);
err_pci_iomap:
free_netdev(netdev);
@@ -2917,6 +3049,9 @@ static void __devexit atl1_remove(struct pci_dev *pdev)
{
struct net_device *netdev = pci_get_drvdata(pdev);
struct atl1_adapter *adapter = netdev_priv(netdev);
+#ifdef CONFIG_ATL1_NAPI
+ int i;
+#endif
/*
* Some atl1 boards lack persistent storage for their MAC, and get it
@@ -2934,6 +3069,12 @@ static void __devexit atl1_remove(struct pci_dev *pdev)
del_timer_sync(&adapter->phy_config_timer);
flush_scheduled_work();
unregister_netdev(netdev);
+
+#ifdef CONFIG_ATL1_NAPI
+ for (i = 0; i < adapter->num_rx_queues; i++)
+ dev_put(&adapter->polling_netdev[i]);
+ kfree(adapter->polling_netdev);
+#endif
atl1_force_ps(&adapter->hw);
pci_iounmap(pdev, adapter->hw.hw_addr);
pci_release_regions(pdev);
diff --git a/drivers/net/atlx/atl1.h b/drivers/net/atlx/atl1.h
index 5187f74..a1757a9 100644
--- a/drivers/net/atlx/atl1.h
+++ b/drivers/net/atlx/atl1.h
@@ -63,6 +63,9 @@ static void atl1_set_mac_addr(struct atl1_hw *hw);
static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
int cmd);
static u32 atl1_check_link(struct atl1_adapter *adapter);
+#ifdef CONFIG_ATL1_NAPI
+static int atl1_clean(struct napi_struct *napi, int budget);
+#endif
extern const struct ethtool_ops atl1_ethtool_ops;
@@ -288,6 +291,15 @@ extern const struct ethtool_ops atl1_ethtool_ops;
ISR_CMB_TX |\
ISR_CMB_RX)
+#define IMR_NONRX_MASK (\
+ ISR_MANUAL |\
+ ISR_SMB |\
+ ISR_GPHY |\
+ ISR_PHY_LINKDOWN|\
+ ISR_DMAR_TO_RST |\
+ ISR_DMAW_TO_RST |\
+ ISR_CMB_TX)
+
#define ISR_TX_EVENT (\
ISR_TXF_UNRUN |\
ISR_TX_PKT |\
@@ -606,6 +618,10 @@ enum atl1_dma_req_block {
#define ATL1_MAX_RFD 2048
#define ATL1_REG_COUNT 1538
+#ifdef CONFIG_ATL1_NAPI
+#define ATL1_NAPI_WEIGHT 64
+#endif
+
#define ATL1_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i]))
#define ATL1_RFD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_free_desc)
#define ATL1_TPD_DESC(R, i) ATL1_GET_DESC(R, i, struct tx_packet_desc)
@@ -818,6 +834,10 @@ struct atl1_adapter {
struct atl1_cmb cmb;
unsigned long flags;
int num_rx_queues;
+#ifdef CONFIG_ATL1_NAPI
+ struct napi_struct napi;
+ struct net_device *polling_netdev;
+#endif
};
enum atl1_state {
diff --git a/drivers/net/atlx/atlx.h b/drivers/net/atlx/atlx.h
index 352432e..18021d9 100644
--- a/drivers/net/atlx/atlx.h
+++ b/drivers/net/atlx/atlx.h
@@ -29,7 +29,12 @@
#include <linux/module.h>
#include <linux/types.h>
-#define ATLX_DRIVER_VERSION "2.1.1"
+#ifndef CONFIG_ATL1_NAPI
+#define DRIVERNAPI
+#else
+#define DRIVERNAPI "-NAPI"
+#endif
+#define ATLX_DRIVER_VERSION "2.1.1"DRIVERNAPI
MODULE_AUTHOR("Xiong Huang <xiong.huang@atheros.com>, \
Chris Snook <csnook@redhat.com>, Jay Cliburn <jcliburn@gmail.com>");
MODULE_LICENSE("GPL");
--
1.5.3.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH 25/26] atl1: add NAPI support
2008-01-01 2:22 ` [PATCH 25/26] atl1: add NAPI support Jay Cliburn
@ 2008-01-01 5:58 ` Stephen Hemminger
0 siblings, 0 replies; 30+ messages in thread
From: Stephen Hemminger @ 2008-01-01 5:58 UTC (permalink / raw)
To: Jay Cliburn; +Cc: netdev
On Mon, 31 Dec 2007 20:22:52 -0600
Jay Cliburn <jacliburn@bellsouth.net> wrote:
> Add support for NAPI, styled after the e1000 NAPI implementation. That we
> follow the e1000 for NAPI shouldn't come as much of a surprise, since the
> entire atl1 driver is based heavily upon it.
>
> Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net>
> ---
> drivers/net/Kconfig | 14 ++++
> drivers/net/atlx/atl1.c | 151 +++++++++++++++++++++++++++++++++++++++++++++--
> drivers/net/atlx/atl1.h | 20 ++++++
> drivers/net/atlx/atlx.h | 7 ++-
> 4 files changed, 186 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
> index d9107e5..095629f 100644
> --- a/drivers/net/Kconfig
> +++ b/drivers/net/Kconfig
> @@ -2371,6 +2371,20 @@ config ATL1
> To compile this driver as a module, choose M here. The module
> will be called atl1.
>
> +config ATL1_NAPI
> + bool "Use Rx Polling (NAPI) (EXPERIMENTAL)"
> + depends on ATL1 && EXPERIMENTAL
> + help
> + NAPI is a new driver API designed to reduce CPU and interrupt load
> + when the driver is receiving lots of packets from the card. It is
> + still somewhat experimental and thus not yet enabled by default.
> +
> + If your estimated Rx load is 10kpps or more, or if the card will be
> + deployed on potentially unfriendly networks (e.g. in a firewall),
> + then say Y here.
> +
> + If in doubt, say N.
> +
> endif # NETDEV_1000
>
> #
> diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
> index 237622e..10bccf6 100644
> --- a/drivers/net/atlx/atl1.c
> +++ b/drivers/net/atlx/atl1.c
> @@ -756,7 +756,16 @@ static void atl1_set_mac_addr(struct atl1_hw *hw)
>
> static int atl1_alloc_queues(struct atl1_adapter *adapter)
> {
> - /* temporary placeholder function for NAPI */
> +#ifdef CONFIG_ATL1_NAPI
> + int size;
> +
> + size = sizeof(struct net_device) * adapter->num_rx_queues;
> + adapter->polling_netdev = kmalloc(size, GFP_KERNEL);
> + if (!adapter->polling_netdev)
> + return -ENOMEM;
> +
> + memset(adapter->polling_netdev, 0, size);
> +#endif
You don't need to allocate pseudo-devices anymore in 2.6.24 or later.
rework to just use napi structures.
--
Stephen Hemminger <stephen.hemminger@vyatta.com>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 26/26] atl1: remove experimental tag and clean up comments
2008-01-01 2:22 [PATCH 00/26] atl1: divide and modernize Jay Cliburn
` (24 preceding siblings ...)
2008-01-01 2:22 ` [PATCH 25/26] atl1: add NAPI support Jay Cliburn
@ 2008-01-01 2:22 ` Jay Cliburn
2008-01-01 17:58 ` [PATCH 00/26] atl1: divide and modernize Christoph Hellwig
26 siblings, 0 replies; 30+ messages in thread
From: Jay Cliburn @ 2008-01-01 2:22 UTC (permalink / raw)
To: netdev; +Cc: Jay Cliburn
All major netdevice functionality is now present in the atl1 driver. As
a result, remove the EXPERIMENTAL Kconfig tag in the main driver, but leave
it in the NAPI driver.
Signed-off-by: Jay Cliburn <jacliburn@bellsouth.net>
---
drivers/net/Kconfig | 4 ++--
drivers/net/atlx/atl1.c | 8 ++------
drivers/net/atlx/atl1.h | 2 +-
drivers/net/atlx/atlx.c | 5 ++---
drivers/net/atlx/atlx.h | 5 ++---
5 files changed, 9 insertions(+), 15 deletions(-)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 095629f..638b90d 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2361,8 +2361,8 @@ config QLA3XXX
will be called qla3xxx.
config ATL1
- tristate "Attansic L1 Gigabit Ethernet support (EXPERIMENTAL)"
- depends on PCI && EXPERIMENTAL
+ tristate "Attansic L1 Gigabit Ethernet support"
+ depends on PCI
select CRC32
select MII
help
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index 10bccf6..411cd82 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -1,7 +1,7 @@
/*
* Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
* Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
- * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
+ * Copyright(c) 2006 - 2007 Jay Cliburn <jcliburn@gmail.com>
*
* Derived from Intel e1000 driver
* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
@@ -31,13 +31,9 @@
* Chris Snook <csnook@redhat.com>
* Jay Cliburn <jcliburn@gmail.com>
*
- * This version is adapted from the Attansic reference driver for
- * inclusion in the Linux kernel. It is currently under heavy development.
- * A very incomplete list of things that need to be dealt with:
+ * This version is adapted from the Attansic reference driver.
*
* TODO:
- * Wake on LAN.
- * Add more ethtool functions.
* Fix abstruse irq enable/disable condition described here:
* http://marc.theaimsgroup.com/?l=linux-netdev&m=116398508500553&w=2
*
diff --git a/drivers/net/atlx/atl1.h b/drivers/net/atlx/atl1.h
index a1757a9..82129be 100644
--- a/drivers/net/atlx/atl1.h
+++ b/drivers/net/atlx/atl1.h
@@ -1,7 +1,7 @@
/*
* Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
* Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
- * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
+ * Copyright(c) 2006 - 2007 Jay Cliburn <jcliburn@gmail.com>
*
* Derived from Intel e1000 driver
* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
diff --git a/drivers/net/atlx/atlx.c b/drivers/net/atlx/atlx.c
index 9cc9441..fb3dd7a 100644
--- a/drivers/net/atlx/atlx.c
+++ b/drivers/net/atlx/atlx.c
@@ -1,8 +1,7 @@
-/* atlx.c -- common functions for Attansic network drivers
- *
+/*
* Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
* Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
- * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
+ * Copyright(c) 2006 - 2007 Jay Cliburn <jcliburn@gmail.com>
* Copyright(c) 2007 Atheros Corporation. All rights reserved.
*
* Derived from Intel e1000 driver
diff --git a/drivers/net/atlx/atlx.h b/drivers/net/atlx/atlx.h
index 18021d9..3c39b27 100644
--- a/drivers/net/atlx/atlx.h
+++ b/drivers/net/atlx/atlx.h
@@ -1,8 +1,7 @@
-/* atlx_hw.h -- common hardware definitions for Attansic network drivers
- *
+/*
* Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
* Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
- * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
+ * Copyright(c) 2006 - 2007 Jay Cliburn <jcliburn@gmail.com>
* Copyright(c) 2007 Atheros Corporation. All rights reserved.
*
* Derived from Intel e1000 driver
--
1.5.3.3
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH 00/26] atl1: divide and modernize
2008-01-01 2:22 [PATCH 00/26] atl1: divide and modernize Jay Cliburn
` (25 preceding siblings ...)
2008-01-01 2:22 ` [PATCH 26/26] atl1: remove experimental tag and clean up comments Jay Cliburn
@ 2008-01-01 17:58 ` Christoph Hellwig
2008-01-01 18:12 ` Jay Cliburn
26 siblings, 1 reply; 30+ messages in thread
From: Christoph Hellwig @ 2008-01-01 17:58 UTC (permalink / raw)
To: Jay Cliburn; +Cc: netdev
On Mon, Dec 31, 2007 at 08:22:27PM -0600, Jay Cliburn wrote:
>
> [Neglected to cc netdev in the first wave.]
>
> Hello Jeff,
>
> Happy New Year to you and all.
>
> In preparation for a future atl2 driver for the Atheros L2 10/100 chip,
> we propose to move the existing atl1 driver to a new directory
> (drivers/net/atlx), then split out functions and definitions that both
> atl1 and atl2 can share. The final structure will look like this:
>
> directory or file status
> ======================= ==========================
> drivers/net/atl1/ deleted
> drivers/net/atlx/ new
> drivers/net/atlx/atl1.c atl1-specific functions
> drivers/net/atlx/atl1.h atl1-specific definitions
> drivers/net/atlx/atlx.c atl1-atl2 shared functions
> drivers/net/atlx/atlx.h atl1-atl2 shared definitions
>
> The first two patches submitted in this patchset accomplish the relocation
> by movng the atl1 driver -- lock, stock, and barrel -- over to
> drivers/net/atlx, then splitting out shareable functions and definitions.
> Some transitory hackery will be present until the atl2 merge. Please
> overlook it for now.
>
> The remaining 24 patches bring the atl1 driver up to par with the current
> vendor driver version 1.2.40.2. NAPI support is included and it seems
> to work, but it needs to be scrutinized by an experienced eye. I had a
> hard time finding much current NAPI documentation, so I just hacked at
> it by looking at the e1000 driver.
How much shared code is going to be there in the end? Unless it's a lot
I fear that the maintaince burden far outweights the benefit of having
shared code.
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH 00/26] atl1: divide and modernize
2008-01-01 17:58 ` [PATCH 00/26] atl1: divide and modernize Christoph Hellwig
@ 2008-01-01 18:12 ` Jay Cliburn
0 siblings, 0 replies; 30+ messages in thread
From: Jay Cliburn @ 2008-01-01 18:12 UTC (permalink / raw)
To: Christoph Hellwig; +Cc: netdev, Chris Snook
On Tue, 1 Jan 2008 17:58:40 +0000
Christoph Hellwig <hch@infradead.org> wrote:
> On Mon, Dec 31, 2007 at 08:22:27PM -0600, Jay Cliburn wrote:
> > The first two patches submitted in this patchset accomplish the
> > relocation by movng the atl1 driver -- lock, stock, and barrel --
> > over to drivers/net/atlx, then splitting out shareable functions
> > and definitions. Some transitory hackery will be present until the
> > atl2 merge. Please overlook it for now.
> How much shared code is going to be there in the end? Unless it's a
> lot I fear that the maintaince burden far outweights the benefit of
> having shared code.
Christoph,
I'm not working on the atl2 merge other than to make accommodations for
it within atl1. I've added Chris Snook to the cc list; he's working on
atl2.
Jay
^ permalink raw reply [flat|nested] 30+ messages in thread