Re: [PATCH 002/002] de2104x: support for systems lacking cache coherence

[David Miller <davem@davemloft.net>]

From: Krzysztof Halasa <khc@pm.waw.pl>
Date: Tue, 10 Feb 2009 02:45:46 +0100

> David Miller <davem@davemloft.net> writes:
> 
> > The issue are descriptors that are _written_ by both the cpu
> > and the device.  That is the problematic case here.
> 
> Do you mean both CPU and 21040 write to the same descriptor at (nearly)
> the same time? Is it TX, RX or both?
> 
> I wonder, how would the patch help it?

The problem is when the chip is writing to one neighbouring descriptor
of one which the cpu is writing to at the same time.

> The patch seems to align the descriptors on cache line boundary. That
> IMHO means the corruption is caused by the 21040 writing to e.g. desc
> #0, CPU writing to desc #1, which causes the cache line write bringing
> the old desc #0 back.

Right.

> Is it possible to use uncached memory for coherent allocations (with no
> write side effects) on this machine?

Good question.