* [net-2.6 PATCH 1/2] ixgbe: Fix DCB traffic class mapping for 82599 @ 2009-04-17 1:00 Jeff Kirsher 2009-04-17 1:00 ` [net-2.6 PATCH 2/2] ixgbe: Fix the DCB PFC thresholds " Jeff Kirsher 2009-04-17 8:17 ` [net-2.6 PATCH 1/2] ixgbe: Fix DCB traffic class mapping " David Miller 0 siblings, 2 replies; 4+ messages in thread From: Jeff Kirsher @ 2009-04-17 1:00 UTC (permalink / raw) To: davem; +Cc: netdev, gospo, Peter P Waskiewicz Jr, stable, Jeff Kirsher From: PJ Waskiewicz <peter.p.waskiewicz.jr@intel.com> The traffic classes in hardware are not symmetrical for Rx and Tx. Rx is every 16 descriptor queues, Tx is not. It runs 32-32-16-16-8-8-8 when running with 8 traffic classes, and runs 64-32-16 when running with 4 traffic classes. This patch fixes the mapping. Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Cc: stable@kernel.org Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> --- drivers/net/ixgbe/ixgbe_main.c | 52 +++++++++++++++++++++++++++++++++++++--- 1 files changed, 48 insertions(+), 4 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c index 49a9037..0188425 100644 --- a/drivers/net/ixgbe/ixgbe_main.c +++ b/drivers/net/ixgbe/ixgbe_main.c @@ -2841,11 +2841,55 @@ static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) } ret = true; } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { - for (i = 0; i < dcb_i; i++) { - adapter->rx_ring[i].reg_idx = i << 4; - adapter->tx_ring[i].reg_idx = i << 4; + if (dcb_i == 8) { + /* + * Tx TC0 starts at: descriptor queue 0 + * Tx TC1 starts at: descriptor queue 32 + * Tx TC2 starts at: descriptor queue 64 + * Tx TC3 starts at: descriptor queue 80 + * Tx TC4 starts at: descriptor queue 96 + * Tx TC5 starts at: descriptor queue 104 + * Tx TC6 starts at: descriptor queue 112 + * Tx TC7 starts at: descriptor queue 120 + * + * Rx TC0-TC7 are offset by 16 queues each + */ + for (i = 0; i < 3; i++) { + adapter->tx_ring[i].reg_idx = i << 5; + adapter->rx_ring[i].reg_idx = i << 4; + } + for ( ; i < 5; i++) { + adapter->tx_ring[i].reg_idx = + ((i + 2) << 4); + adapter->rx_ring[i].reg_idx = i << 4; + } + for ( ; i < dcb_i; i++) { + adapter->tx_ring[i].reg_idx = + ((i + 8) << 3); + adapter->rx_ring[i].reg_idx = i << 4; + } + + ret = true; + } else if (dcb_i == 4) { + /* + * Tx TC0 starts at: descriptor queue 0 + * Tx TC1 starts at: descriptor queue 64 + * Tx TC2 starts at: descriptor queue 96 + * Tx TC3 starts at: descriptor queue 112 + * + * Rx TC0-TC3 are offset by 32 queues each + */ + adapter->tx_ring[0].reg_idx = 0; + adapter->tx_ring[1].reg_idx = 64; + adapter->tx_ring[2].reg_idx = 96; + adapter->tx_ring[3].reg_idx = 112; + for (i = 0 ; i < dcb_i; i++) + adapter->rx_ring[i].reg_idx = i << 5; + + ret = true; + } else { + ret = false; } - ret = true; } else { ret = false; } ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [net-2.6 PATCH 2/2] ixgbe: Fix the DCB PFC thresholds for 82599 2009-04-17 1:00 [net-2.6 PATCH 1/2] ixgbe: Fix DCB traffic class mapping for 82599 Jeff Kirsher @ 2009-04-17 1:00 ` Jeff Kirsher 2009-04-17 8:17 ` David Miller 2009-04-17 8:17 ` [net-2.6 PATCH 1/2] ixgbe: Fix DCB traffic class mapping " David Miller 1 sibling, 1 reply; 4+ messages in thread From: Jeff Kirsher @ 2009-04-17 1:00 UTC (permalink / raw) To: davem; +Cc: netdev, gospo, Peter P Waskiewicz Jr, Jeff Kirsher From: PJ Waskiewicz <peter.p.waskiewicz.jr@intel.com> The thresholds for the DCB priority flow control are incorrect for 82599. This fixes the thresholds to be correct. Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> --- drivers/net/ixgbe/ixgbe_dcb_82599.c | 28 +++++++++++++++++----------- 1 files changed, 17 insertions(+), 11 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_dcb_82599.c b/drivers/net/ixgbe/ixgbe_dcb_82599.c index 470b676..f4417fc 100644 --- a/drivers/net/ixgbe/ixgbe_dcb_82599.c +++ b/drivers/net/ixgbe/ixgbe_dcb_82599.c @@ -290,7 +290,7 @@ s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw, s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config) { - u32 i, reg; + u32 i, reg, rx_pba_size; /* If PFC is disabled globally then fall back to LFC. */ if (!dcb_config->pfc_mode_enable) { @@ -301,17 +301,23 @@ s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, /* Configure PFC Tx thresholds per TC */ for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { - /* Config and remember Tx */ + if (dcb_config->rx_pba_cfg == pba_equal) + rx_pba_size = IXGBE_RXPBSIZE_64KB; + else + rx_pba_size = (i < 4) ? IXGBE_RXPBSIZE_80KB + : IXGBE_RXPBSIZE_48KB; + + reg = ((rx_pba_size >> 5) & 0xFFE0); if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full || - dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx) { - reg = hw->fc.high_water | IXGBE_FCRTH_FCEN; - IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg); - reg = hw->fc.low_water | IXGBE_FCRTL_XONE; - IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), reg); - } else { - IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), 0); - IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); - } + dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx) + reg |= IXGBE_FCRTL_XONE; + IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), reg); + + reg = ((rx_pba_size >> 2) & 0xFFE0); + if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full || + dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx) + reg |= IXGBE_FCRTH_FCEN; + IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg); } /* Configure pause time (2 TCs per register) */ ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [net-2.6 PATCH 2/2] ixgbe: Fix the DCB PFC thresholds for 82599 2009-04-17 1:00 ` [net-2.6 PATCH 2/2] ixgbe: Fix the DCB PFC thresholds " Jeff Kirsher @ 2009-04-17 8:17 ` David Miller 0 siblings, 0 replies; 4+ messages in thread From: David Miller @ 2009-04-17 8:17 UTC (permalink / raw) To: jeffrey.t.kirsher; +Cc: netdev, gospo, peter.p.waskiewicz.jr From: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Date: Thu, 16 Apr 2009 18:00:41 -0700 > The thresholds for the DCB priority flow control are incorrect for 82599. > This fixes the thresholds to be correct. > > Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> > Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Applied. ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [net-2.6 PATCH 1/2] ixgbe: Fix DCB traffic class mapping for 82599 2009-04-17 1:00 [net-2.6 PATCH 1/2] ixgbe: Fix DCB traffic class mapping for 82599 Jeff Kirsher 2009-04-17 1:00 ` [net-2.6 PATCH 2/2] ixgbe: Fix the DCB PFC thresholds " Jeff Kirsher @ 2009-04-17 8:17 ` David Miller 1 sibling, 0 replies; 4+ messages in thread From: David Miller @ 2009-04-17 8:17 UTC (permalink / raw) To: jeffrey.t.kirsher; +Cc: netdev, gospo, peter.p.waskiewicz.jr, stable From: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Date: Thu, 16 Apr 2009 18:00:20 -0700 > The traffic classes in hardware are not symmetrical for Rx and Tx. Rx > is every 16 descriptor queues, Tx is not. It runs 32-32-16-16-8-8-8 when > running with 8 traffic classes, and runs 64-32-16 when running with 4 > traffic classes. This patch fixes the mapping. > > Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> > Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Applied. ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2009-04-17 8:18 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2009-04-17 1:00 [net-2.6 PATCH 1/2] ixgbe: Fix DCB traffic class mapping for 82599 Jeff Kirsher 2009-04-17 1:00 ` [net-2.6 PATCH 2/2] ixgbe: Fix the DCB PFC thresholds " Jeff Kirsher 2009-04-17 8:17 ` David Miller 2009-04-17 8:17 ` [net-2.6 PATCH 1/2] ixgbe: Fix DCB traffic class mapping " David Miller
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