From: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
To: davem@davemloft.net
Cc: netdev@vger.kernel.org,
Alexander Duyck <alexander.h.duyck@intel.com>,
Bruce Allan <bruce.w.allan@intel.com>,
Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Subject: [net-next-2.6 PATCH 4/4] igb/e1000e: update PSSR_MDIX value to reflect correct bit
Date: Tue, 26 May 2009 16:51:05 -0700 [thread overview]
Message-ID: <20090526235105.28231.39406.stgit@localhost.localdomain> (raw)
In-Reply-To: <20090526234958.28231.16894.stgit@localhost.localdomain>
From: Alexander Duyck <alexander.h.duyck@intel.com>
The phy port status register has the MDI-X status bit on bit 11, not bit 3
as is currently setup in the define. This patch corrects that so the
correct bit is checked on igp PHY types.
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Acked-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
---
drivers/net/e1000e/hw.h | 2 +-
drivers/net/igb/e1000_phy.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/e1000e/hw.h b/drivers/net/e1000e/hw.h
index d8b8229..6cdb703 100644
--- a/drivers/net/e1000e/hw.h
+++ b/drivers/net/e1000e/hw.h
@@ -253,7 +253,7 @@ enum e1e_registers {
#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
-#define IGP01E1000_PSSR_MDIX 0x0008
+#define IGP01E1000_PSSR_MDIX 0x0800
#define IGP01E1000_PSSR_SPEED_MASK 0xC000
#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
diff --git a/drivers/net/igb/e1000_phy.h b/drivers/net/igb/e1000_phy.h
index 3228a86..ebe4b61 100644
--- a/drivers/net/igb/e1000_phy.h
+++ b/drivers/net/igb/e1000_phy.h
@@ -80,7 +80,7 @@ s32 igb_phy_init_script_igp3(struct e1000_hw *hw);
#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
-#define IGP01E1000_PSSR_MDIX 0x0008
+#define IGP01E1000_PSSR_MDIX 0x0800
#define IGP01E1000_PSSR_SPEED_MASK 0xC000
#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
#define IGP02E1000_PHY_CHANNEL_NUM 4
next prev parent reply other threads:[~2009-05-26 23:51 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-05-26 23:50 [net-next-2.6 PATCH 1/4] igb: add RQDPC (Receive Queue Drop Packet Count) register macro Jeff Kirsher
2009-05-26 23:50 ` [net-next-2.6 PATCH 2/4] igb: Implement reading of reg RQDPC (Receive Queue Drop Packet Count) Jeff Kirsher
2009-05-27 3:36 ` David Miller
2009-05-26 23:50 ` [net-next-2.6 PATCH 3/4] igb: Record host memory receive overflow in net_stats Jeff Kirsher
2009-05-27 3:36 ` David Miller
2009-05-26 23:51 ` Jeff Kirsher [this message]
2009-05-27 3:36 ` [net-next-2.6 PATCH 4/4] igb/e1000e: update PSSR_MDIX value to reflect correct bit David Miller
2009-05-27 3:36 ` [net-next-2.6 PATCH 1/4] igb: add RQDPC (Receive Queue Drop Packet Count) register macro David Miller
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