[PATCH 1/2 net-next-2.6] cxgb3: fix EDC filename string

[PATCH 1/2 net-next-2.6] cxgb3: fix EDC filename string

[Divy Le Ray]

From: Divy Le Ray <divy@chelsio.com>

Fix a cut'n paste error in the AEL2020 twinax EDC file name

Signed-off-by: Divy Le Ray <divy@chelsio.com>
---

 drivers/net/cxgb3/cxgb3_main.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)


diff --git a/drivers/net/cxgb3/cxgb3_main.c b/drivers/net/cxgb3/cxgb3_main.c
index ec05149..8b3e76c 100644
--- a/drivers/net/cxgb3/cxgb3_main.c
+++ b/drivers/net/cxgb3/cxgb3_main.c
@@ -993,7 +993,7 @@ static int bind_qsets(struct adapter *adap)
 #define TPSRAM_NAME "cxgb3/t3%c_psram-%d.%d.%d.bin"
 #define AEL2005_OPT_EDC_NAME "cxgb3/ael2005_opt_edc.bin"
 #define AEL2005_TWX_EDC_NAME "cxgb3/ael2005_twx_edc.bin"
-#define AEL2020_TWX_EDC_NAME "cxgb3/ael2005_twx_edc.bin"
+#define AEL2020_TWX_EDC_NAME "cxgb3/ael2020_twx_edc.bin"
 
 static inline const char *get_edc_fw_name(int edc_idx)
 {

[PATCH 2/2 net-next-2.6] cxgb3: fix Gen2 pci default settings

[Divy Le Ray]

From: Divy Le Ray <divy@chelsio.com>

Modify control register settings to accommodate the bridge's max read requset
size.

Signed-off-by: Divy Le Ray <divy@chelsio.com>
---

 drivers/net/cxgb3/t3_hw.c |   13 ++++++++++++-
 1 files changed, 12 insertions(+), 1 deletions(-)


diff --git a/drivers/net/cxgb3/t3_hw.c b/drivers/net/cxgb3/t3_hw.c
index e78d341..526e144 100644
--- a/drivers/net/cxgb3/t3_hw.c
+++ b/drivers/net/cxgb3/t3_hw.c
@@ -3465,7 +3465,7 @@ static void config_pcie(struct adapter *adap)
 		{201, 321, 258, 450, 834, 1602}
 	};
 
-	u16 val;
+	u16 val, devid;
 	unsigned int log2_width, pldsize;
 	unsigned int fst_trn_rx, fst_trn_tx, acklat, rpllmt;
 
@@ -3473,6 +3473,17 @@ static void config_pcie(struct adapter *adap)
 			     adap->params.pci.pcie_cap_addr + PCI_EXP_DEVCTL,
 			     &val);
 	pldsize = (val & PCI_EXP_DEVCTL_PAYLOAD) >> 5;
+
+	pci_read_config_word(adap->pdev, 0x2, &devid);
+	if (devid == 0x37) {
+		pci_write_config_word(adap->pdev,
+				      adap->params.pci.pcie_cap_addr +
+				      PCI_EXP_DEVCTL,
+				      val & ~PCI_EXP_DEVCTL_READRQ &
+				      ~PCI_EXP_DEVCTL_PAYLOAD);
+		pldsize = 0;
+	}
+
 	pci_read_config_word(adap->pdev,
 			     adap->params.pci.pcie_cap_addr + PCI_EXP_LNKCTL,
 			     &val);

Re: [PATCH 1/2 net-next-2.6] cxgb3: fix EDC filename string

[David Miller]

From: Divy Le Ray <divy@chelsio.com>
Date: Fri, 31 Jul 2009 00:23:34 -0700

> From: Divy Le Ray <divy@chelsio.com>
> 
> Fix a cut'n paste error in the AEL2020 twinax EDC file name
> 
> Signed-off-by: Divy Le Ray <divy@chelsio.com>

Applied.

Re: [PATCH 2/2 net-next-2.6] cxgb3: fix Gen2 pci default settings

[David Miller]

From: Divy Le Ray <divy@chelsio.com>
Date: Fri, 31 Jul 2009 00:23:39 -0700

> From: Divy Le Ray <divy@chelsio.com>
> 
> Modify control register settings to accommodate the bridge's max read requset
> size.
> 
> Signed-off-by: Divy Le Ray <divy@chelsio.com>

Applied.