[PATCH] tc35815: Disable PM capability

[PATCH] tc35815: Disable PM capability

[Atsushi Nemoto]

This chip may report existance of PM registers though they are not
supported.  Disable PM features by clearing pdev->pm_cap.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
---
 drivers/net/tc35815.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/drivers/net/tc35815.c b/drivers/net/tc35815.c
index d2ca47f..71e4482 100644
--- a/drivers/net/tc35815.c
+++ b/drivers/net/tc35815.c
@@ -909,6 +909,11 @@ static int __devinit tc35815_init_one(struct pci_dev *pdev,
 	lp = netdev_priv(dev);
 	lp->dev = dev;
 
+	/* This device may have PM registers but they are not supported. */
+	if (pdev->pm_cap) {
+		dev_info(&pdev->dev, "Disable PM\n");
+		pdev->pm_cap = 0;
+	}
 	/* enable device (incl. PCI PM wakeup), and bus-mastering */
 	rc = pcim_enable_device(pdev);
 	if (rc)
-- 
1.5.6.5

Re: [PATCH] tc35815: Disable PM capability

[David Miller]

From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Date: Thu,  3 Sep 2009 00:51:20 +0900

> This chip may report existance of PM registers though they are not
> supported.  Disable PM features by clearing pdev->pm_cap.
> 
> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>

Please handle this as a quirk in drivers/pci/quirks.c as that
is the proper place to handle these kinds of exceptions.

The patch should be submitted to the PCI subsystem maintainer.

Thanks!

Re: [PATCH] tc35815: Disable PM capability

[Atsushi Nemoto]

On Wed, 02 Sep 2009 23:15:03 -0700 (PDT), David Miller <davem@davemloft.net> wrote:
> > This chip may report existance of PM registers though they are not
> > supported.  Disable PM features by clearing pdev->pm_cap.
> > 
> > Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
> 
> Please handle this as a quirk in drivers/pci/quirks.c as that
> is the proper place to handle these kinds of exceptions.
> 
> The patch should be submitted to the PCI subsystem maintainer.

Thanks, I will add quirks to MIPS arch code because this fixup is
required only for internal ether controller in TXx9 SoCs.

---
Atsushi Nemoto