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From: David Miller <davem@davemloft.net>
To: aabdulla@nvidia.com
Cc: manfred@colorfullife.com, akpm@osdl.org, netdev@vger.kernel.org
Subject: Re: [PATCH] forcedeth: updated phy errata
Date: Wed, 02 Sep 2009 23:22:01 -0700 (PDT)	[thread overview]
Message-ID: <20090902.232201.248326790.davem@davemloft.net> (raw)
In-Reply-To: <4A9C57F5.10800@nvidia.com>

From: Ayaz Abdulla <aabdulla@nvidia.com>
Date: Mon, 31 Aug 2009 19:08:37 -0400

> This patch updates the special programming (and/or errata) needed in
> order to setup the phy for various vendor models.
> 
> The new models include:
> Marvell E1116
> Marvell E1111
> Marvell E1011
> Marvell E3016
> Broadcom 9507
> Broadcom AC131
> Broadcom 50610
> 
> Signed-off-by: Ayaz Abdulla <aabdulla@nvidia.com>

Please document what these individual bits mean which you
are clearing, by using an individual define for each register
bit to describe it's purpose, and then define the mask as
a concatenation of these bits.

Having an opaque bitmask is not how to do this.

Thanks.

  reply	other threads:[~2009-09-03  6:21 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-08-31 23:08 [PATCH] forcedeth: updated phy errata Ayaz Abdulla
2009-09-03  6:22 ` David Miller [this message]
2009-09-04 13:57   ` Ayaz Abdulla
2009-09-04 22:00     ` David Miller
2009-09-04 17:22       ` Ayaz Abdulla
2009-09-04 22:54         ` David Miller

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