From mboxrd@z Thu Jan  1 00:00:00 1970
From: David Miller <davem@davemloft.net>
Subject: Re: [PATCH] forcedeth: updated phy errata
Date: Wed, 02 Sep 2009 23:22:01 -0700 (PDT)
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From: Ayaz Abdulla <aabdulla@nvidia.com>
Date: Mon, 31 Aug 2009 19:08:37 -0400

> This patch updates the special programming (and/or errata) needed in
> order to setup the phy for various vendor models.
> 
> The new models include:
> Marvell E1116
> Marvell E1111
> Marvell E1011
> Marvell E3016
> Broadcom 9507
> Broadcom AC131
> Broadcom 50610
> 
> Signed-off-by: Ayaz Abdulla <aabdulla@nvidia.com>

Please document what these individual bits mean which you
are clearing, by using an individual define for each register
bit to describe it's purpose, and then define the mask as
a concatenation of these bits.

Having an opaque bitmask is not how to do this.

Thanks.