* [net-next-2.6 PATCH] igb: add support for reporting 5GT/s during probe on PCIe Gen2
@ 2010-04-09 19:52 Jeff Kirsher
2010-04-09 23:54 ` Ben Hutchings
0 siblings, 1 reply; 5+ messages in thread
From: Jeff Kirsher @ 2010-04-09 19:52 UTC (permalink / raw)
To: davem; +Cc: netdev, gospo, Alexander Duyck, Jeff Kirsher
From: Alexander Duyck <alexander.h.duyck@intel.com>
This change corrects the fact that we were not reporting Gen2 link speeds
when we were in fact connected at Gen2 rates.
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
---
drivers/net/igb/e1000_defines.h | 3 +++
drivers/net/igb/e1000_mac.c | 19 ++++++++++++++++---
drivers/net/igb/igb_main.c | 1 +
3 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/net/igb/e1000_defines.h b/drivers/net/igb/e1000_defines.h
index 31d24e0..8e440e8 100644
--- a/drivers/net/igb/e1000_defines.h
+++ b/drivers/net/igb/e1000_defines.h
@@ -615,6 +615,9 @@
#define PCIE_LINK_WIDTH_MASK 0x3F0
#define PCIE_LINK_WIDTH_SHIFT 4
+#define PCIE_LINK_SPEED_MASK 0x0F
+#define PCIE_LINK_SPEED_2500 0x01
+#define PCIE_LINK_SPEED_5000 0x02
#define PCIE_DEVICE_CONTROL2_16ms 0x0005
#define PHY_REVISION_MASK 0xFFFFFFF0
diff --git a/drivers/net/igb/e1000_mac.c b/drivers/net/igb/e1000_mac.c
index be8d010..4371835 100644
--- a/drivers/net/igb/e1000_mac.c
+++ b/drivers/net/igb/e1000_mac.c
@@ -53,17 +53,30 @@ s32 igb_get_bus_info_pcie(struct e1000_hw *hw)
u16 pcie_link_status;
bus->type = e1000_bus_type_pci_express;
- bus->speed = e1000_bus_speed_2500;
ret_val = igb_read_pcie_cap_reg(hw,
PCIE_LINK_STATUS,
&pcie_link_status);
- if (ret_val)
+ if (ret_val) {
bus->width = e1000_bus_width_unknown;
- else
+ bus->speed = e1000_bus_speed_unknown;
+ } else {
+ switch (pcie_link_status & PCIE_LINK_SPEED_MASK) {
+ case PCIE_LINK_SPEED_2500:
+ bus->speed = e1000_bus_speed_2500;
+ break;
+ case PCIE_LINK_SPEED_5000:
+ bus->speed = e1000_bus_speed_5000;
+ break;
+ default:
+ bus->speed = e1000_bus_speed_unknown;
+ break;
+ }
+
bus->width = (enum e1000_bus_width)((pcie_link_status &
PCIE_LINK_WIDTH_MASK) >>
PCIE_LINK_WIDTH_SHIFT);
+ }
reg = rd32(E1000_STATUS);
bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
diff --git a/drivers/net/igb/igb_main.c b/drivers/net/igb/igb_main.c
index 876a49b..a3c79ad 100644
--- a/drivers/net/igb/igb_main.c
+++ b/drivers/net/igb/igb_main.c
@@ -1637,6 +1637,7 @@ static int __devinit igb_probe(struct pci_dev *pdev,
dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
netdev->name,
((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
+ (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
"unknown"),
((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
(hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [net-next-2.6 PATCH] igb: add support for reporting 5GT/s during probe on PCIe Gen2
2010-04-09 19:52 [net-next-2.6 PATCH] igb: add support for reporting 5GT/s during probe on PCIe Gen2 Jeff Kirsher
@ 2010-04-09 23:54 ` Ben Hutchings
2010-04-13 9:58 ` David Miller
0 siblings, 1 reply; 5+ messages in thread
From: Ben Hutchings @ 2010-04-09 23:54 UTC (permalink / raw)
To: Jeff Kirsher; +Cc: davem, netdev, gospo, Alexander Duyck
On Fri, 2010-04-09 at 12:52 -0700, Jeff Kirsher wrote:
> From: Alexander Duyck <alexander.h.duyck@intel.com>
>
> This change corrects the fact that we were not reporting Gen2 link speeds
> when we were in fact connected at Gen2 rates.
>
> Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
> ---
>
> drivers/net/igb/e1000_defines.h | 3 +++
> drivers/net/igb/e1000_mac.c | 19 ++++++++++++++++---
> drivers/net/igb/igb_main.c | 1 +
> 3 files changed, 20 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/net/igb/e1000_defines.h b/drivers/net/igb/e1000_defines.h
> index 31d24e0..8e440e8 100644
> --- a/drivers/net/igb/e1000_defines.h
> +++ b/drivers/net/igb/e1000_defines.h
> @@ -615,6 +615,9 @@
>
> #define PCIE_LINK_WIDTH_MASK 0x3F0
> #define PCIE_LINK_WIDTH_SHIFT 4
> +#define PCIE_LINK_SPEED_MASK 0x0F
> +#define PCIE_LINK_SPEED_2500 0x01
> +#define PCIE_LINK_SPEED_5000 0x02
> #define PCIE_DEVICE_CONTROL2_16ms 0x0005
[...]
These generic definitions belong in <linux/pci_regs.h>; in fact some of
it is already there.
Ben.
--
Ben Hutchings, Senior Software Engineer, Solarflare Communications
Not speaking for my employer; that's the marketing department's job.
They asked us to note that Solarflare product names are trademarked.
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [net-next-2.6 PATCH] igb: add support for reporting 5GT/s during probe on PCIe Gen2
2010-04-09 23:54 ` Ben Hutchings
@ 2010-04-13 9:58 ` David Miller
0 siblings, 0 replies; 5+ messages in thread
From: David Miller @ 2010-04-13 9:58 UTC (permalink / raw)
To: bhutchings; +Cc: jeffrey.t.kirsher, netdev, gospo, alexander.h.duyck
From: Ben Hutchings <bhutchings@solarflare.com>
Date: Sat, 10 Apr 2010 00:54:16 +0100
> On Fri, 2010-04-09 at 12:52 -0700, Jeff Kirsher wrote:
>> From: Alexander Duyck <alexander.h.duyck@intel.com>
>>
>> This change corrects the fact that we were not reporting Gen2 link speeds
>> when we were in fact connected at Gen2 rates.
>>
>> Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
>> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
>> ---
>>
>> drivers/net/igb/e1000_defines.h | 3 +++
>> drivers/net/igb/e1000_mac.c | 19 ++++++++++++++++---
>> drivers/net/igb/igb_main.c | 1 +
>> 3 files changed, 20 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/net/igb/e1000_defines.h b/drivers/net/igb/e1000_defines.h
>> index 31d24e0..8e440e8 100644
>> --- a/drivers/net/igb/e1000_defines.h
>> +++ b/drivers/net/igb/e1000_defines.h
>> @@ -615,6 +615,9 @@
>>
>> #define PCIE_LINK_WIDTH_MASK 0x3F0
>> #define PCIE_LINK_WIDTH_SHIFT 4
>> +#define PCIE_LINK_SPEED_MASK 0x0F
>> +#define PCIE_LINK_SPEED_2500 0x01
>> +#define PCIE_LINK_SPEED_5000 0x02
>> #define PCIE_DEVICE_CONTROL2_16ms 0x0005
> [...]
>
> These generic definitions belong in <linux/pci_regs.h>; in fact some of
> it is already there.
Agreed, please put these in the PCI header file.
^ permalink raw reply [flat|nested] 5+ messages in thread
* [net-next-2.6 PATCH] igb: add support for reporting 5GT/s during probe on PCIe Gen2
@ 2010-04-27 11:02 Jeff Kirsher
2010-04-27 19:55 ` David Miller
0 siblings, 1 reply; 5+ messages in thread
From: Jeff Kirsher @ 2010-04-27 11:02 UTC (permalink / raw)
To: davem; +Cc: netdev, gospo, Alexander Duyck, Jeff Kirsher
From: Alexander Duyck <alexander.h.duyck@intel.com>
This change corrects the fact that we were not reporting Gen2 link speeds
when we were in fact connected at Gen2 rates.
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
---
drivers/net/igb/e1000_defines.h | 4 ----
drivers/net/igb/e1000_mac.c | 27 ++++++++++++++++++++-------
drivers/net/igb/igb_main.c | 1 +
include/linux/pci_regs.h | 3 +++
4 files changed, 24 insertions(+), 11 deletions(-)
diff --git a/drivers/net/igb/e1000_defines.h b/drivers/net/igb/e1000_defines.h
index 31d24e0..24d9be6 100644
--- a/drivers/net/igb/e1000_defines.h
+++ b/drivers/net/igb/e1000_defines.h
@@ -610,11 +610,7 @@
#define IGP_LED3_MODE 0x07000000
/* PCI/PCI-X/PCI-EX Config space */
-#define PCIE_LINK_STATUS 0x12
#define PCIE_DEVICE_CONTROL2 0x28
-
-#define PCIE_LINK_WIDTH_MASK 0x3F0
-#define PCIE_LINK_WIDTH_SHIFT 4
#define PCIE_DEVICE_CONTROL2_16ms 0x0005
#define PHY_REVISION_MASK 0xFFFFFFF0
diff --git a/drivers/net/igb/e1000_mac.c b/drivers/net/igb/e1000_mac.c
index be8d010..90c5e01 100644
--- a/drivers/net/igb/e1000_mac.c
+++ b/drivers/net/igb/e1000_mac.c
@@ -53,17 +53,30 @@ s32 igb_get_bus_info_pcie(struct e1000_hw *hw)
u16 pcie_link_status;
bus->type = e1000_bus_type_pci_express;
- bus->speed = e1000_bus_speed_2500;
ret_val = igb_read_pcie_cap_reg(hw,
- PCIE_LINK_STATUS,
- &pcie_link_status);
- if (ret_val)
+ PCI_EXP_LNKSTA,
+ &pcie_link_status);
+ if (ret_val) {
bus->width = e1000_bus_width_unknown;
- else
+ bus->speed = e1000_bus_speed_unknown;
+ } else {
+ switch (pcie_link_status & PCI_EXP_LNKSTA_CLS) {
+ case PCI_EXP_LNKSTA_CLS_2_5GB:
+ bus->speed = e1000_bus_speed_2500;
+ break;
+ case PCI_EXP_LNKSTA_CLS_5_0GB:
+ bus->speed = e1000_bus_speed_5000;
+ break;
+ default:
+ bus->speed = e1000_bus_speed_unknown;
+ break;
+ }
+
bus->width = (enum e1000_bus_width)((pcie_link_status &
- PCIE_LINK_WIDTH_MASK) >>
- PCIE_LINK_WIDTH_SHIFT);
+ PCI_EXP_LNKSTA_NLW) >>
+ PCI_EXP_LNKSTA_NLW_SHIFT);
+ }
reg = rd32(E1000_STATUS);
bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
diff --git a/drivers/net/igb/igb_main.c b/drivers/net/igb/igb_main.c
index a14303a..919e363 100644
--- a/drivers/net/igb/igb_main.c
+++ b/drivers/net/igb/igb_main.c
@@ -1638,6 +1638,7 @@ static int __devinit igb_probe(struct pci_dev *pdev,
dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
netdev->name,
((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
+ (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
"unknown"),
((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
(hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index c8f3029..c4c3d68 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -442,7 +442,10 @@
#define PCI_EXP_LNKCTL_LABIE 0x0800 /* Lnk Autonomous Bandwidth Interrupt Enable */
#define PCI_EXP_LNKSTA 18 /* Link Status */
#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */
+#define PCI_EXP_LNKSTA_CLS_2_5GB 0x01 /* Current Link Speed 2.5GT/s */
+#define PCI_EXP_LNKSTA_CLS_5_0GB 0x02 /* Current Link Speed 5.0GT/s */
#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Nogotiated Link Width */
+#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */
#define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */
#define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */
#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [net-next-2.6 PATCH] igb: add support for reporting 5GT/s during probe on PCIe Gen2
2010-04-27 11:02 Jeff Kirsher
@ 2010-04-27 19:55 ` David Miller
0 siblings, 0 replies; 5+ messages in thread
From: David Miller @ 2010-04-27 19:55 UTC (permalink / raw)
To: jeffrey.t.kirsher; +Cc: netdev, gospo, alexander.h.duyck
From: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Date: Tue, 27 Apr 2010 04:02:40 -0700
> From: Alexander Duyck <alexander.h.duyck@intel.com>
>
> This change corrects the fact that we were not reporting Gen2 link speeds
> when we were in fact connected at Gen2 rates.
>
> Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Applied.
^ permalink raw reply [flat|nested] 5+ messages in thread
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2010-04-09 19:52 [net-next-2.6 PATCH] igb: add support for reporting 5GT/s during probe on PCIe Gen2 Jeff Kirsher
2010-04-09 23:54 ` Ben Hutchings
2010-04-13 9:58 ` David Miller
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2010-04-27 19:55 ` David Miller
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