From: David Miller <davem@davemloft.net>
To: sathyap@serverengines.com
Cc: netdev@vger.kernel.org
Subject: Re: [net-next-2.6 PATCH] be2net: memory barrier fixes on IBM p7 platform
Date: Wed, 30 Jun 2010 13:27:49 -0700 (PDT) [thread overview]
Message-ID: <20100630.132749.218066997.davem@davemloft.net> (raw)
In-Reply-To: <20100629101117.GA2338@serverengines.com>
From: Sathya Perla <sathyap@serverengines.com>
Date: Tue, 29 Jun 2010 15:41:17 +0530
> The ibm p7 architecure seems to reorder memory accesses more
> aggressively than previous ppc64 architectures. This requires memory
> barriers to ensure that rx/tx doorbells are pressed only after
> memory to be DMAed is written.
>
> Signed-off-by: Sathya Perla <sathyap@serverengines.com>
Applied, but I had to fix something:
> @@ -972,7 +976,8 @@ static struct be_eth_rx_compl *be_rx_compl_get(struct be_adapter *adapter)
>
> if (rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] == 0)
> return NULL;
> -
> +
> + rmb();
That first addition does nothing but add erroneous trailing
whitespace.
You can physically see that something must be wrong here just by look
at this patch chunk, please review things more thoroughly before
submitting in the future.
Thanks.
next prev parent reply other threads:[~2010-06-30 20:27 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-06-29 10:11 [net-next-2.6 PATCH] be2net: memory barrier fixes on IBM p7 platform Sathya Perla
2010-06-30 20:27 ` David Miller [this message]
2010-07-01 6:23 ` Sathya Perla
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