From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andi Kleen Subject: Re: [PATCH] atomic: add atomic_inc_not_zero_hint() Date: Mon, 15 Nov 2010 15:39:07 +0100 Message-ID: <20101115143907.GN7269@basil.fritz.box> References: <20101105110828.52f061b3.akpm@linux-foundation.org> <1288981224.2882.1105.camel@edumazet-laptop> <20101105112821.57f80481.akpm@linux-foundation.org> <1288984844.2665.52.camel@edumazet-laptop> <20101105195101.GC15561@linux.vnet.ibm.com> <20101113222612.GD2825@linux.vnet.ibm.com> <1289830636.2607.70.camel@edumazet-laptop> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: Eric Dumazet , "Paul E. McKenney" , Andrew Morton , linux-kernel , David Miller , netdev , Arnaldo Carvalho de Melo , Ingo Molnar , Andi Kleen , Nick Piggin To: Christoph Lameter Return-path: Received: from one.firstfloor.org ([213.235.205.2]:54222 "EHLO one.firstfloor.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755874Ab0KOOjJ (ORCPT ); Mon, 15 Nov 2010 09:39:09 -0500 Content-Disposition: inline In-Reply-To: Sender: netdev-owner@vger.kernel.org List-ID: > > atomic_read() and atomic_cmpxchg(). We tried prefetchw() and it was a > > performance drop. It was with only 16 cpus contending on neighbour > > Does prefetchw work? Andi claims that prefetchw is not working on > x86 and I doubt that you ran tests on Itanium. AMD supports it due to their MOESI protocol, but it's not supported in MESIF as used by Intel QPI. The kernel maps it on Intel to ordinary prefetch. -Andi -- ak@linux.intel.com -- Speaking for myself only.