From: David Miller <davem@davemloft.net>
To: romieu@fr.zoreil.com
Cc: cantona@cantona.no-ip.org, hayeswang@realtek.com,
linux-kernel@vger.kernel.org, nic_swsd@realtek.com,
netdev@vger.kernel.org
Subject: Re: [PATCH 1/1] r8169.c correct MSIEnable register offset
Date: Thu, 15 Dec 2011 01:43:59 -0500 (EST) [thread overview]
Message-ID: <20111215.014359.1153990753442293322.davem@davemloft.net> (raw)
In-Reply-To: <20111214213713.GA2907@electric-eye.fr.zoreil.com>
From: Francois Romieu <romieu@fr.zoreil.com>
Date: Wed, 14 Dec 2011 22:37:13 +0100
> Su Kang Yin <cantona@cantona.no-ip.org> :
>> correct MSIEnable (bit 5) register to Config1 (offset 0x52) instead of
>> Config2 (offset 0x53)
>
> I wonder where the inspiration for the MSIEnable bit came from.
> It looks like something was confused with the Message Control word
> in PCI space.
>
> Imho you can simply remove it altogether.
Someone should find out what the real situation is with this.
Maybe it mirrors the PCI config space setting and is read-only, maybe
not. But it should be determined for sure before changing this. :-)
next prev parent reply other threads:[~2011-12-15 6:43 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-12-14 7:13 [PATCH 1/1] r8169.c correct MSIEnable register offset Su Kang Yin
2011-12-14 21:37 ` Francois Romieu
2011-12-15 6:43 ` David Miller [this message]
2011-12-15 8:34 ` hayeswang
2011-12-15 18:37 ` [PATCH] r8169: fix Config2 MSIEnable bit setting Francois Romieu
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