From mboxrd@z Thu Jan  1 00:00:00 1970
From: David Miller <davem@davemloft.net>
Subject: Re: [PATCH 2/2] net: emaclite: add barriers to support Xilinx Zynq
 platform
Date: Sun, 01 Dec 2013 20:09:06 -0500 (EST)
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To: srikanth.thokala@xilinx.com
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From: Srikanth Thokala <srikanth.thokala@xilinx.com>
Date: Thu, 28 Nov 2013 12:59:57 +0530

> This patch adds barriers at appropriate places to ensure the driver
> works on Xilinx Zynq ARM-based SoC platform.
> 
> Signed-off-by: Srikanth Thokala <sthokal@xilinx.com>

Memory barriers must have comments.

Specifically, the comment must describe what exactly is being ensured
by the memory barrier.  What entity must see what memory operations in
what order?