From: David Miller <davem@davemloft.net>
To: bhelgaas@google.com
Cc: jesse.brandeburg@gmail.com, linux-pci@vger.kernel.org,
jeffrey.t.kirsher@intel.com, netdev@vger.kernel.org,
gospo@redhat.com, sassmann@redhat.com,
linux-kernel@vger.kernel.org, bjorn.helgaas@hp.com
Subject: Re: [net-next] pci_regs.h: Add PCI bus link speed and width defines
Date: Fri, 03 Jan 2014 19:30:08 -0500 (EST) [thread overview]
Message-ID: <20140103.193008.684316024702680161.davem@davemloft.net> (raw)
In-Reply-To: <CAErSpo7TJXTCxpFKWXLTaHmqXXnYQdnpNeWt+cehSaES2Jh30w@mail.gmail.com>
From: Bjorn Helgaas <bhelgaas@google.com>
Date: Fri, 3 Jan 2014 17:00:42 -0700
> On Fri, Jan 3, 2014 at 4:56 PM, David Miller <davem@davemloft.net> wrote:
>> From: Bjorn Helgaas <bhelgaas@google.com>
>> Date: Fri, 3 Jan 2014 15:15:57 -0700
>>
>>> However, I do raise my eyebrows a bit at drivers that poke around in
>>> the PCIe capability. I would prefer to have PCI core interfaces that
>>> handle that instead. But I haven't seen Jeff's changes yet.
>>
>> The changes just read the link status to interpret the speed at which
>> the PCI-E link is running at.
>
> Several drivers want to do that. It'd be nice if somebody abstracted
> that out somehow. Jacob added pcie_get_minimum_link() which is
> similar. But maybe Jeff needs something more in this case.
>
> In any case, it's not a blocker for this patch.
Ok.
Jeff, please merge this via the Intel submission process and don't forget
to add Bjorn's ACK.
Thanks.
next prev parent reply other threads:[~2014-01-04 0:30 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-28 12:36 [net-next] pci_regs.h: Add PCI bus link speed and width defines Jeff Kirsher
2014-01-03 0:21 ` David Miller
2014-01-03 21:53 ` Jesse Brandeburg
2014-01-03 22:15 ` Bjorn Helgaas
2014-01-03 23:56 ` David Miller
2014-01-04 0:00 ` Bjorn Helgaas
2014-01-04 0:30 ` David Miller [this message]
2014-01-04 1:27 ` Jeff Kirsher
2014-01-04 1:48 ` David Miller
2014-01-04 1:51 ` Jeff Kirsher
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